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[209.132.180.67]) by mx.google.com with ESMTP id 4-v6si5904948pgf.684.2018.04.30.00.49.13; Mon, 30 Apr 2018 00:49:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752355AbeD3HtC (ORCPT + 99 others); Mon, 30 Apr 2018 03:49:02 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:3359 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752063AbeD3Hs7 (ORCPT ); Mon, 30 Apr 2018 03:48:59 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Mon, 30 Apr 2018 00:49:07 -0700 Received: from HQMAIL108.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 30 Apr 2018 00:48:56 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 30 Apr 2018 00:48:56 -0700 Received: from UKMAIL102.nvidia.com (10.26.138.15) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Mon, 30 Apr 2018 07:48:58 +0000 Received: from tbergstrom-lnx.Nvidia.com (10.21.24.170) by UKMAIL102.nvidia.com (10.26.138.15) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Mon, 30 Apr 2018 07:48:54 +0000 Received: by tbergstrom-lnx.Nvidia.com (Postfix, from userid 1002) id 7F0CDF8077F; Mon, 30 Apr 2018 10:48:54 +0300 (EEST) Date: Mon, 30 Apr 2018 10:48:54 +0300 From: Peter De Schrijver To: Dmitry Osipenko CC: Thierry Reding , Jonathan Hunter , Prashant Gaikwad , Stephen Boyd , Michael Turquette , "Linus Walleij" , Marcel Ziswiler , Marc Dietrich , , , , Subject: Re: [PATCH v1 1/4] clk: tegra20: Add DEV1/DEV2 OSC dividers Message-ID: <20180430074854.GM6835@tbergstrom-lnx.Nvidia.com> References: <20180426235818.10018-1-digetx@gmail.com> <20180426235818.10018-2-digetx@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20180426235818.10018-2-digetx@gmail.com> X-NVConfidentiality: public User-Agent: Mutt/1.5.21 (2010-09-15) X-Originating-IP: [10.21.24.170] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL102.nvidia.com (10.26.138.15) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Apr 27, 2018 at 02:58:15AM +0300, Dmitry Osipenko wrote: > CDEV1/CDEV2 clocks could have corresponding oscillator clock divider as > a parent. Add these dividers in order to be able to provide that parent > option. > > Signed-off-by: Dmitry Osipenko > --- > drivers/clk/tegra/clk-tegra20.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c > index 0ee56dd04cec..16cf4108f2ff 100644 > --- a/drivers/clk/tegra/clk-tegra20.c > +++ b/drivers/clk/tegra/clk-tegra20.c > @@ -26,6 +26,8 @@ > #include "clk.h" > #include "clk-id.h" > > +#define MISC_CLK_ENB 0x48 > + > #define OSC_CTRL 0x50 > #define OSC_CTRL_OSC_FREQ_MASK (3<<30) > #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30) > @@ -831,6 +833,16 @@ static void __init tegra20_periph_clk_init(void) > periph_clk_enb_refcnt); > clks[TEGRA20_CLK_PEX] = clk; > > + /* cdev1 OSC divider */ > + clk_register_divider(NULL, "cdev1_osc_div", "clk_m", > + 0, clk_base + MISC_CLK_ENB, 20, 2, > + CLK_DIVIDER_POWER_OF_TWO, NULL); > + I don't know if this divider can be changed glitchlessly so to be safe, I would mark this readonly, so add the CLK_DIVIDER_READ_ONLY flag. > + /* cdev2 OSC divider */ > + clk_register_divider(NULL, "cdev2_osc_div", "clk_m", > + 0, clk_base + MISC_CLK_ENB, 22, 2, > + CLK_DIVIDER_POWER_OF_TWO, NULL); > + > /* cdev1 */ > clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, 0, 26000000); > clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0, > -- > 2.17.0 > Peter.