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[209.132.180.67]) by mx.google.com with ESMTP id w11-v6si5816878pgq.333.2018.04.30.02.49.17; Mon, 30 Apr 2018 02:49:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753161AbeD3Jsi (ORCPT + 99 others); Mon, 30 Apr 2018 05:48:38 -0400 Received: from mail.skyhub.de ([5.9.137.197]:33414 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752601AbeD3Jsg (ORCPT ); Mon, 30 Apr 2018 05:48:36 -0400 X-Virus-Scanned: Nedap ESD1 at mail.skyhub.de Received: from mail.skyhub.de ([127.0.0.1]) by localhost (blast.alien8.de [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id FrESL0x_Rpr2; Mon, 30 Apr 2018 11:48:19 +0200 (CEST) Received: from pd.tnic (p200300EC2BC6BB0018CA5EB1E28A3112.dip0.t-ipconnect.de [IPv6:2003:ec:2bc6:bb00:18ca:5eb1:e28a:3112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.skyhub.de (SuperMail on ZX Spectrum 128k) with ESMTPSA id 925BF1EC00E5; Mon, 30 Apr 2018 11:48:19 +0200 (CEST) Date: Mon, 30 Apr 2018 11:48:02 +0200 From: Borislav Petkov To: David Wang Cc: tony.luck@intel.com, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, gregkh@linuxfoundation.org, x86@kernel.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org, brucechang@via-alliance.com, cooperyan@zhaoxin.com, qiyuanwang@zhaoxin.com, benjaminpan@viatech.com, lukelin@viacpu.com, timguo@zhaoxin.com Subject: Re: [PATCH v3 2/2] x86/mce: add CMCI support for Centaur CPUs Message-ID: <20180430094802.GF6509@pd.tnic> References: <1524652420-17330-1-git-send-email-davidwang@zhaoxin.com> <1524652420-17330-3-git-send-email-davidwang@zhaoxin.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1524652420-17330-3-git-send-email-davidwang@zhaoxin.com> User-Agent: Mutt/1.9.3 (2018-01-21) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Apr 25, 2018 at 06:33:40PM +0800, David Wang wrote: > Newer Centaur support CMCI mechnism, which is compatible with INTEL CMCI. > > Signed-off-by: David Wang > --- > arch/x86/kernel/cpu/mcheck/mce.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c > index 38ccab8..f9a7295 100644 > --- a/arch/x86/kernel/cpu/mcheck/mce.c > +++ b/arch/x86/kernel/cpu/mcheck/mce.c > @@ -1757,6 +1757,8 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) > } > case X86_VENDOR_CENTAUR: > mce_centaur_feature_init(c); > + mce_intel_feature_init(c); > + mce_adjust_timer = cmci_intel_adjust_timer; This won't work in configs with CONFIG_X86_MCE_INTEL disabled. You need to define CONFIG_X86_MCE_CENTAUR or so which depends on CONFIG_CPU_SUP_CENTAUR and CONFIG_X86_MCE_INTEL and which then makes sure the intel CMCI et al stuff is enabled. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.