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[209.132.180.67]) by mx.google.com with ESMTP id g3-v6si7038292pld.309.2018.04.30.04.43.35; Mon, 30 Apr 2018 04:43:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=YhxKJa1j; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754130AbeD3Lm4 (ORCPT + 99 others); Mon, 30 Apr 2018 07:42:56 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:46457 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752534AbeD3Lmw (ORCPT ); Mon, 30 Apr 2018 07:42:52 -0400 Received: by mail-pf0-f195.google.com with SMTP id p12so6532365pff.13 for ; Mon, 30 Apr 2018 04:42:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jFB4gf1Utj1KIZxbtbvpo9BdsJZSspuQL9e3AoWW1oM=; b=YhxKJa1javifVoKZZ+EjRixZtnbvVDa6O7jIXW5lBquCmY6jRW5UYqOfVW6TzjCINl I/N9OINoFhIvrAbB7u7otZwiEv4QsqNB0e3Z8ZoyGKxJIQ8wiycfoZWZ1Tz0i66KyV65 AinDjQe7bc3/KHWU2eopFATC1KF4smFxosZgc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jFB4gf1Utj1KIZxbtbvpo9BdsJZSspuQL9e3AoWW1oM=; b=ZxExOYuBHIk7siFfcKNzw5xpqjRuxxOrZrKQXrhi9M3e33rgiKwyJFgacFgH+vIce7 PZuduT8pR1GJ/FYkYZLvzIMuqstb7xLRBrGxs3vnEBoF/ipXIrOJZCiVZPY1lk4myJZc CIJcyjyEvnPqjOmxOvWopb/1U9sk9bN+SEWmbon0r18ZHxbnCMfvQld2CvCmEs038y4Z 4i48OGvP+8BV2acC/kJ3w+4cAamj4CSsjjAi0mlOejMVF12fzGUZRHFDdg/1ZwIKkYvp AVjgSsVW65HVU/4aibb9h/Xa6N/C1AD6bK6Pe7YFjvtNmwkMSykxDxAsEy5lLdblEn1R ptuQ== X-Gm-Message-State: ALQs6tD8gc0Affeuxfyc7HALaJMn2ZimtD/58nggtneEXm4X+1N9s67S usdo00UqhdYT1AKGhQgQCkrwlg== X-Received: by 2002:a17:902:82c3:: with SMTP id u3-v6mr12067745plz.83.1525088572353; Mon, 30 Apr 2018 04:42:52 -0700 (PDT) Received: from localhost.localdomain ([183.82.224.14]) by smtp.gmail.com with ESMTPSA id s17sm16762357pfi.165.2018.04.30.04.42.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 30 Apr 2018 04:42:51 -0700 (PDT) From: Jagan Teki To: Maxime Ripard Cc: Chen-Yu Tsai , Icenowy Zheng , Jernej Skrabec , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , David Airlie , dri-devel@lists.freedesktop.org, Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Michael Trimarchi , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jagan Teki Subject: [PATCH 15/21] drm: sun4i: add support for HVCC regulator for DWC HDMI glue Date: Mon, 30 Apr 2018 17:10:52 +0530 Message-Id: <20180430114058.5061-16-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180430114058.5061-1-jagan@amarulasolutions.com> References: <20180430114058.5061-1-jagan@amarulasolutions.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Icenowy Zheng Allwinner SoCs with DWC HDMI controller have a "HVCC" power pin for the HDMI part, and on some boards it's connected to a dedicated regulator rather than the main 3.3v. Add support for optional HVCC regulator. For boards that doesn't use a dedicated regulator to power it, the default dummy regulator is used. Signed-off-by: Icenowy Zheng Signed-off-by: Jagan Teki --- drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 14 ++++++++++++++ drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 ++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c index 9f40a44b456b..7c33faff7ad4 100644 --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c @@ -73,6 +73,12 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master, if (encoder->possible_crtcs == 0) return -EPROBE_DEFER; + hdmi->vcc_hdmi = devm_regulator_get(dev, "hvcc"); + if (IS_ERR(hdmi->vcc_hdmi)) { + dev_err(dev, "Could not get HDMI power supply\n"); + return PTR_ERR(hdmi->vcc_hdmi); + } + hdmi->rst_ctrl = devm_reset_control_get(dev, "ctrl"); if (IS_ERR(hdmi->rst_ctrl)) { dev_err(dev, "Could not get ctrl reset control\n"); @@ -91,6 +97,12 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master, return ret; } + ret = regulator_enable(hdmi->vcc_hdmi); + if (ret) { + dev_err(dev, "Cannot enable HDMI power supply\n"); + goto err_disable_vcc; + } + ret = clk_prepare_enable(hdmi->clk_tmds); if (ret) { dev_err(dev, "Could not enable tmds clock\n"); @@ -143,6 +155,8 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master, clk_disable_unprepare(hdmi->clk_tmds); err_assert_ctrl_reset: reset_control_assert(hdmi->rst_ctrl); +err_disable_vcc: + regulator_disable(hdmi->vcc_hdmi); return ret; } diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h index 79154f0f674a..c25d75ef9303 100644 --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h @@ -10,6 +10,7 @@ #include #include #include +#include #include #define SUN8I_HDMI_PHY_DBG_CTRL_REG 0x0000 @@ -173,6 +174,7 @@ struct sun8i_dw_hdmi { struct drm_encoder encoder; struct sun8i_hdmi_phy *phy; struct dw_hdmi_plat_data plat_data; + struct regulator *vcc_hdmi; struct reset_control *rst_ctrl; }; -- 2.14.3