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[209.132.180.67]) by mx.google.com with ESMTP id o2-v6si6403989pgq.451.2018.04.30.09.20.57; Mon, 30 Apr 2018 09:21:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=Wi8oS6Kt; dkim=pass header.i=@codeaurora.org header.s=default header.b=dS2jThip; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754850AbeD3QUr (ORCPT + 99 others); Mon, 30 Apr 2018 12:20:47 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:49620 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753334AbeD3QUm (ORCPT ); Mon, 30 Apr 2018 12:20:42 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 935C960712; Mon, 30 Apr 2018 16:20:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1525105241; bh=JJpxk4WIhc55433kPkC+1/y96W0297ACAltylOPgaq8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Wi8oS6KtBYM4SXQ8ZhjOhYmSaMICGgpWDF/7O3B+LNC7PgmB9hHaMWeowjUjfDUw/ J8d5+VCpqTt1Tg8VaMJ/85vxLuWkniX2azJcQuQns8TtX8miQi65o/mOPXqYWcwo7S 0KQ2Q5LaVAxE8nF2NYMQ3aUw6xBI1WXyjaEzbZ9o= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from anischal-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: anischal@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 72F7A6074C; Mon, 30 Apr 2018 16:20:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1525105240; bh=JJpxk4WIhc55433kPkC+1/y96W0297ACAltylOPgaq8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dS2jThip0ek/JiOXh40RlO6GE+62YVQe/0DYtDugSzrvk2VkX4DfpYeYvpt8CUiub itQKvH3decAKFiOJo2Cgl508bdZwBeDFUqSRsyQxnG1te8joYKJEK94B0NwYZJK5wA W8NWIMaHBRbSBguBOe+jiOuL7zmasJnL1zPVnYZ8= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 72F7A6074C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=anischal@codeaurora.org From: Amit Nischal To: Stephen Boyd , Michael Turquette Cc: Andy Gross , David Brown , Rajendra Nayak , Odelu Kukatla , Taniya Das , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Amit Nischal Subject: [PATCH v6 2/3] clk: qcom: Add support for BRANCH_NO_DELAY flag for branch clocks Date: Mon, 30 Apr 2018 21:50:09 +0530 Message-Id: <1525105210-8689-3-git-send-email-anischal@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1525105210-8689-1-git-send-email-anischal@codeaurora.org> References: <1525105210-8689-1-git-send-email-anischal@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There could be few clocks where the clock status bit is not required to be polled as the clock on/off would be controlled by enabling/disabling external source. Add support for the same by introducing new flag named as 'BRANCH_NO_DELAY'. Signed-off-by: Amit Nischal --- drivers/clk/qcom/clk-branch.c | 7 +++++-- drivers/clk/qcom/clk-branch.h | 1 + 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c index 26f7af31..1a3db39 100644 --- a/drivers/clk/qcom/clk-branch.c +++ b/drivers/clk/qcom/clk-branch.c @@ -77,8 +77,11 @@ static int clk_branch_wait(const struct clk_branch *br, bool enabling, bool voted = br->halt_check & BRANCH_VOTED; const char *name = clk_hw_get_name(&br->clkr.hw); - /* Skip checking halt bit if the clock is in hardware gated mode */ - if (clk_branch_in_hwcg_mode(br)) + /* + * Skip checking halt bit if halt_check is BRANCH_NO_DELAY or + * the clock is in hardware gated mode + */ + if (br->halt_check == BRANCH_NO_DELAY || clk_branch_in_hwcg_mode(br)) return 0; if (br->halt_check == BRANCH_HALT_DELAY || (!enabling && voted)) { diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index 284df3f..5d621f3 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -42,6 +42,7 @@ struct clk_branch { #define BRANCH_HALT_ENABLE 1 /* pol: 0 = halt */ #define BRANCH_HALT_ENABLE_VOTED (BRANCH_HALT_ENABLE | BRANCH_VOTED) #define BRANCH_HALT_DELAY 2 /* No bit to check; just delay */ +#define BRANCH_NO_DELAY 3 /* No bit to check; without delay */ struct clk_regmap clkr; }; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation