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[209.132.180.67]) by mx.google.com with ESMTP id u20si7606902pfm.70.2018.04.30.09.22.00; Mon, 30 Apr 2018 09:22:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=QfvRSoq+; dkim=pass header.i=@codeaurora.org header.s=default header.b=KSggp0gI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754749AbeD3QUd (ORCPT + 99 others); Mon, 30 Apr 2018 12:20:33 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:49382 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753334AbeD3QUa (ORCPT ); Mon, 30 Apr 2018 12:20:30 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 2B4A060C65; Mon, 30 Apr 2018 16:20:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1525105230; bh=u32SaOf/zTINR7gWAJJQe/WkREbCNk9bQmOPTrHxOlM=; h=From:To:Cc:Subject:Date:From; b=QfvRSoq+0IKfhegOKKk5iJq/S+EpwoYzpCK2MJ+wLThMdQF6x4eiEg230lyEHPR10 fXzID8O4zlyZSjnpMXCRKDtpvseet1n4HobWdcqcaccxCI8lIlNX5B1c9OQ0slmfRy VAF1X9fnsNi8TVQ0Kbt8rPBEUNV2tiBSroF05YAM= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from anischal-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: anischal@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 7A7196074C; Mon, 30 Apr 2018 16:20:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1525105229; bh=u32SaOf/zTINR7gWAJJQe/WkREbCNk9bQmOPTrHxOlM=; h=From:To:Cc:Subject:Date:From; b=KSggp0gI8Qbhr3o/EfQzqCUH6iDeMKqRDS001nU/N9wd+vTBwp+++3Oc3KXxLGcaE p8gUy7V4qxp/24McSvMduD9zSokzOGQ4vjdWh/r3ayjBWmCuSIecdKLVaM96dVS3uc mbnxb5s77nipThfs9rJu+iGw519aizhTUZBDyqV8= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 7A7196074C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=anischal@codeaurora.org From: Amit Nischal To: Stephen Boyd , Michael Turquette Cc: Andy Gross , David Brown , Rajendra Nayak , Odelu Kukatla , Taniya Das , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Amit Nischal Subject: [PATCH v6 0/3] Misc patches to support clocks for SDM845 Date: Mon, 30 Apr 2018 21:50:07 +0530 Message-Id: <1525105210-8689-1-git-send-email-anischal@codeaurora.org> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Changes in v6: 1. Adressed review comments for v3 and v4 version of GCC driver for SDM845. https://lkml.org/lkml/2018/4/16/1129. 2. Add support for new flag 'BRANCH_NO_DELAY' for branch clocks. 3. Addressed review comments for v5 version of rcg2_shared_ops patch. https://lkml.org/lkml/2018/4/19/86 4. The GCC clock driver(patch 3) depends upon the below patches related to GDSC operation and RPMh clock driver, which are under review. https://lkml.org/lkml/2018/4/27/110 https://lkml.org/lkml/2018/4/24/390 Changes in v5: 1. Adressed review comments for v3 and v4 version of GCC driver for SDM845 https://lkml.org/lkml/2018/4/16/1129 2. Removed bi_tcxo clock being modelled from the GCC driver, as RPMH clock driver would provide the same. https://lkml.org/lkml/2018/4/13/685 3. The GCC clock driver(patch 2) depends upon the below patches related to GDSC operation and RPMh clock driver, which are under review. https://lkml.org/lkml/2018/4/2/143 https://lkml.org/lkml/2018/4/13/685 Changes in v4: 1. Adressed review comments for v2 version of GCC driver for SDM845 https://lkml.org/lkml/2018/4/9/55. 2. The GCC clock driver(patch 3) depends upon the below patches related to GDSC operation and are under review. https://lkml.org/lkml/2018/4/2/142 Changes in v3: 1. Adressed review comments given for v2 series. 2. The GCC clock driver(patch 3) depends upon the below patches related to GDSC operation and are under review. https://lkml.org/lkml/2018/4/2/142 Changes in v2: Fixup for recalc_rate ops for clk_rcg2_shared_ops: There could be few scenarios where shared clocks are configured at rate other than CXO by boot. In those cases there would be a mismatch between the rate calculated by the recalc shared ops and the actual HW register configuration. Fix the same by adding an additional check to read current src from CFG register and make a decision based on that. Changes in v1: https://lkml.org/lkml/2018/1/31/209 This patch series does the miscellaneous changes to support clock nodes for SDM845. Below are the major changes for which the existing code does not have support. 1. Clear hardware clock control bit of RCGs where HW clock control bit is set by default so that software can control those root clocks. 2. Introduces clk_rcg2_shared_ops to support clock controller drivers for SDM845. With new shared ops, RCGs with shared branches will be configured to a safe source in disable path and actual RCG update configuration will be done in enable path instead of doing config update in set_rate. In set_rate(), just cache the rate instead of doing actual configuration update. Also each RCG in clock controller driver will have their own safe configuration frequency table to switch to safe frequency. 3. Add support for controlling Fabia PLL for which the support is not available in existing alpha PLL code. 4. Add Global Clock controller (GCC) driver for SDM845. This should allow most non-multimedia device drivers to probe and control their clocks. [v1] : https://lkml.org/lkml/2018/1/31/209 [v2] : https://lkml.org/lkml/2018/3/8/495 [v3] : https://www.spinics.net/lists/linux-arm-msm/msg35009.html [v4] : https://lkml.org/lkml/2018/4/9/79 [v5] : https://lkml.org/lkml/2018/4/18/367 Amit Nischal (2): clk: qcom: Configure the RCGs to a safe source as needed clk: qcom: Add support for BRANCH_NO_DELAY flag for branch clocks Taniya Das (1): clk: qcom: Add Global Clock controller (GCC) driver for SDM845 .../devicetree/bindings/clock/qcom,gcc.txt | 1 + drivers/clk/qcom/Kconfig | 10 +- drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-branch.c | 7 +- drivers/clk/qcom/clk-branch.h | 1 + drivers/clk/qcom/clk-rcg.h | 7 +- drivers/clk/qcom/clk-rcg2.c | 207 +- drivers/clk/qcom/gcc-sdm845.c | 3480 ++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sdm845.h | 239 ++ 9 files changed, 3940 insertions(+), 13 deletions(-) create mode 100644 drivers/clk/qcom/gcc-sdm845.c create mode 100644 include/dt-bindings/clock/qcom,gcc-sdm845.h -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation