Received: by 10.192.165.148 with SMTP id m20csp4935185imm; Tue, 1 May 2018 06:31:17 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqtaoYiZPHosLAjTSjfwlNG9BMgE/X8rGCTFDVwiEtMIG5NMYRSlZuNz89FZ/zRYFUY2DzE X-Received: by 2002:a17:902:584:: with SMTP id f4-v6mr16060776plf.290.1525181477113; Tue, 01 May 2018 06:31:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525181477; cv=none; d=google.com; s=arc-20160816; b=mfh7e59x1FgmUTBtYk7L8GMG70HVY/RfJKxZiHRGGZpGOgXqdxIv8KhXriCUoPXAJ0 +SZYnWNxq/1FL6n+d/FM81tQ+6T+xCZSrMdQYEX1DEwtRnXPDUB83c1oPKu/5iPpJlgS muJOHgiveLHfKLg1iF2hw7uSFkwhZ+MorY9iikGedF80hlLVzBRthvEE8VuNeFcF7fR4 DMFeG2tjLkGoOnRJlifngNNnmUlr2qcpsRcSTaUVFVer8rrXP2xWwR7JF7GPbFarqrKF 1dBSP8GDUEQSmeArEYoUHzhfoS5vuKsrYifzDynfndygTsocoY9+plHuzkdUzLHm6Gq/ UViA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding :content-language:in-reply-to:mime-version:user-agent:date :message-id:from:references:cc:to:subject:dkim-signature :arc-authentication-results; bh=5etdrKNp3m97yK2jja1ycdFJdZXgAqO3MMUgKDFeCsU=; b=rk17v6xpFrh3WZ7UeIgSAwiyFqpaSscFuXOE+NiylVErpktmsMwJEL4ftvn+LgPt3x 0LTAZLuMSF/CRQOPxeS4DBKkO/NwdDR1rlO/8B2DisRx3Flp58M2cGkT7MrUb3/8V4E8 OLmzOgvAp2kXkQBMWpNoCXw0VbhWajnUkt4rUFU80q5oxYb/9IYC6iGhM49oOmqK00Ti 6HUTc8UfURVs4UZHsRFqx3pDhl31M9F00rKU7iJoTZ2sVUmlMCGFeI4dfuVKARtftkl9 6IA1BzszDV0zMeK9miJbf80XfX+64nqlNXNInavi5rYq0DTKPQKwg24zz4VqV9DSujVe 70lA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ev996H49; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d29si9539367pfb.232.2018.05.01.06.31.02; Tue, 01 May 2018 06:31:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ev996H49; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755513AbeEAN3R (ORCPT + 99 others); Tue, 1 May 2018 09:29:17 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:42726 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754841AbeEAN3P (ORCPT ); Tue, 1 May 2018 09:29:15 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id w41DS4qL024453; Tue, 1 May 2018 08:28:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1525181284; bh=7/wuCYAjVZr/0UtQmZGPh+ZNAMi6fUcp0bboXXZ/3ig=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=ev996H49GpeZEehkuxYIxu8CvuJk54uDuBbZR/w71OLdT/gOYXydyr3y8Og5ZMhwO RBQhiWQWmQBl8PC/kCU9IEITWEdjST1bvVw4SkqnIWYKETcXj3Oxtx8s7Gzvgo313b UV+kQRUj7XvSlainVg9Y1ibinWov+8Ny3K1OQyoI= Received: from DFLE110.ent.ti.com (dfle110.ent.ti.com [10.64.6.31]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w41DS43U019145; Tue, 1 May 2018 08:28:04 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Tue, 1 May 2018 08:28:03 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Tue, 1 May 2018 08:28:03 -0500 Received: from [172.24.190.172] (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w41DRrAO023008; Tue, 1 May 2018 08:27:55 -0500 Subject: Re: [PATCH v9 01/27] clk: davinci: pll: allow dev == NULL To: David Lechner , , , CC: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Kevin Hilman , Bartosz Golaszewski , Adam Ford , References: <20180427001745.4116-1-david@lechnology.com> <20180427001745.4116-2-david@lechnology.com> From: Sekhar Nori Message-ID: <7f968fd3-eb0e-37ba-9f2d-2b948640ef73@ti.com> Date: Tue, 1 May 2018 18:57:53 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20180427001745.4116-2-david@lechnology.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Friday 27 April 2018 05:47 AM, David Lechner wrote: > This modifies the TI DaVinci PLL clock driver to allow for the case > when dev == NULL. On some (most) SoCs that use this driver, the PLL > clock needs to be registered during early boot because it is used > for clocksource/clockevent and there will be no platform device available. > > Signed-off-by: David Lechner > diff --git a/drivers/clk/davinci/pll.c b/drivers/clk/davinci/pll.c > index 23a24c944f1d..7c4d808b8fdb 100644 > --- a/drivers/clk/davinci/pll.c > +++ b/drivers/clk/davinci/pll.c > @@ -111,6 +111,31 @@ struct davinci_pll_clk { > #define to_davinci_pll_clk(_hw) \ > container_of((_hw), struct davinci_pll_clk, hw) > > +static inline void *_devm_kzalloc(struct device *dev, size_t size, gfp_t flags) > +{ > + if (dev) > + return devm_kzalloc(dev, size, flags); > + > + return kzalloc(size, flags); I would shift to using kzalloc() only. The utility of devm_kzalloc() is gone if you cannot always rely on it since you have to handle the free for the other case. Same thing for other devres APIs below. > +} > + > +static inline void *_devm_kmalloc_array(struct device *dev, size_t n, > + size_t size, gfp_t flags) > +{ > + if (dev) > + return devm_kmalloc_array(dev, n, size, flags); > + > + return kmalloc_array(n, size, flags); > +} > + > +static inline struct clk *_devm_clk_register(struct device *dev, struct clk_hw *hw) > +{ > + if (dev) > + return devm_clk_register(dev, hw); > + > + return clk_register(NULL, hw); > +} > + > diff --git a/drivers/clk/davinci/pll.h b/drivers/clk/davinci/pll.h > index b1b6fb23f972..92a0978a7d29 100644 > --- a/drivers/clk/davinci/pll.h > +++ b/drivers/clk/davinci/pll.h > @@ -11,6 +11,7 @@ > #include > #include > #include > +#include > #include > > #define PLL_HAS_CLKMODE BIT(0) /* PLL has PLLCTL[CLKMODE] */ > @@ -94,7 +95,8 @@ struct davinci_pll_obsclk_info { > struct clk *davinci_pll_clk_register(struct device *dev, > const struct davinci_pll_clk_info *info, > const char *parent_name, > - void __iomem *base); > + void __iomem *base, > + struct regmap *cfgchip); > struct clk *davinci_pll_auxclk_register(struct device *dev, > const char *name, > void __iomem *base); > @@ -110,32 +112,33 @@ davinci_pll_sysclk_register(struct device *dev, > const struct davinci_pll_sysclk_info *info, > void __iomem *base); > > -int of_davinci_pll_init(struct device *dev, > +int of_davinci_pll_init(struct device *dev, struct device_node *node, > const struct davinci_pll_clk_info *info, > const struct davinci_pll_obsclk_info *obsclk_info, > const struct davinci_pll_sysclk_info **div_info, > u8 max_sysclk_id, > - void __iomem *base); > + void __iomem *base, > + struct regmap *cfgchip); > > /* Platform-specific callbacks */ > > -int da830_pll_init(struct device *dev, void __iomem *base); > +int da830_pll_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); > > -int da850_pll0_init(struct device *dev, void __iomem *base); > -int da850_pll1_init(struct device *dev, void __iomem *base); > -int of_da850_pll0_init(struct device *dev, void __iomem *base); > -int of_da850_pll1_init(struct device *dev, void __iomem *base); > +int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); Having this declared both here and in include/linux/clk/davinci.h is strange. Can we include that file directly where its needed? > diff --git a/include/linux/clk/davinci.h b/include/linux/clk/davinci.h > new file mode 100644 > index 000000000000..1298cca509ac > --- /dev/null > +++ b/include/linux/clk/davinci.h > @@ -0,0 +1,24 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Clock driver for TI Davinci PSC controllers PSC/PLL controllers. Thanks, Sekhar