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[209.132.180.67]) by mx.google.com with ESMTP id a6-v6si9319354plz.49.2018.05.01.06.47.37; Tue, 01 May 2018 06:47:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=A1qGsGa5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755131AbeEANr0 (ORCPT + 99 others); Tue, 1 May 2018 09:47:26 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:59003 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754084AbeEANrZ (ORCPT ); Tue, 1 May 2018 09:47:25 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id w41DkLm6021421; Tue, 1 May 2018 08:46:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1525182381; bh=90NHay2VPkCrKA8h/wMJBWKADAwBvM8w3+73COpr2pU=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=A1qGsGa5qC6Q9BaONoDi17ZWRntyCTe75EfTNadCCjuiuuoklXKwh9dRSu0WgfKxj UnA9ZW9JUqCxQMwYbqv1nEWcT/d5unRlxJq6tsv+JWo260b6rTRp6dDI/PMSjnPyuy DSH7nbTKdTAGEPtiX8rNJEbKz/T+dVaTNFzyln3Y= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w41DkLCX025265; Tue, 1 May 2018 08:46:21 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Tue, 1 May 2018 08:46:21 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Tue, 1 May 2018 08:46:21 -0500 Received: from [172.24.190.172] (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w41DkBwd021930; Tue, 1 May 2018 08:46:12 -0500 Subject: Re: [PATCH v9 02/27] clk: davinci: da850-pll: change PLL0 to CLK_OF_DECLARE To: David Lechner , , , CC: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Kevin Hilman , Bartosz Golaszewski , Adam Ford , References: <20180427001745.4116-1-david@lechnology.com> <20180427001745.4116-3-david@lechnology.com> From: Sekhar Nori Message-ID: Date: Tue, 1 May 2018 19:16:10 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20180427001745.4116-3-david@lechnology.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Friday 27 April 2018 05:47 AM, David Lechner wrote: > PLL0 on davinci/da850-type device needs to be registered early in boot > because it is needed for clocksource/clockevent. Change the driver > to use CLK_OF_DECLARE for this special case. > > Signed-off-by: David Lechner > --- > > v9 changes: > - new patch in v9 > > > drivers/clk/davinci/pll-da850.c | 26 ++++++++++++++++++++++---- > drivers/clk/davinci/pll.c | 4 +++- > drivers/clk/davinci/pll.h | 2 +- > 3 files changed, 26 insertions(+), 6 deletions(-) > > diff --git a/drivers/clk/davinci/pll-da850.c b/drivers/clk/davinci/pll-da850.c > index 00a6ece7b524..743527de1da2 100644 > --- a/drivers/clk/davinci/pll-da850.c > +++ b/drivers/clk/davinci/pll-da850.c > @@ -12,6 +12,8 @@ > #include > #include > #include > +#include > +#include > #include > #include > > @@ -135,11 +137,27 @@ static const struct davinci_pll_sysclk_info *da850_pll0_sysclk_info[] = { > NULL > }; > > -int of_da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) > +void of_da850_pll0_init(struct device_node *node) > { > - return of_davinci_pll_init(dev, dev->of_node, &da850_pll0_info, > - &da850_pll0_obsclk_info, > - da850_pll0_sysclk_info, 7, base, cfgchip); > + void __iomem *base; > + struct regmap *cfgchip; > + > + base = of_iomap(node, 0); > + if (!base) { > + pr_err("%s: ioremap failed\n", __func__); > + return; > + } > + > + cfgchip = syscon_regmap_lookup_by_compatible("ti,da830-cfgchip"); > + if (IS_ERR(cfgchip)) { > + pr_warn("%s: failed to get cfgchip (%ld)\n", __func__, > + PTR_ERR(cfgchip)); > + cfgchip = NULL; > + } Is this error handling for cfgchip needed here considering davinci_pll_clk_register() already checks and warns. Thanks, Sekhar