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[209.132.180.67]) by mx.google.com with ESMTP id 7-v6si9450860pll.132.2018.05.01.07.19.51; Tue, 01 May 2018 07:20:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Z2zuels8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755905AbeEAOSR (ORCPT + 99 others); Tue, 1 May 2018 10:18:17 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:44503 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755849AbeEAOSP (ORCPT ); Tue, 1 May 2018 10:18:15 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id w41EHDB9000341; Tue, 1 May 2018 09:17:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1525184233; bh=gGAoOxnTSZXnUWYKn83z68h8yObxUs0DdxA9fwYd/Ww=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=Z2zuels8Kvh78BuFSz1hppMJYSqA3f0YgY3s6xOHrE/wLy894ZmrC5838gk3jTUV4 OZqVxN5jBhYkJu6Z99gYEHNWsSXX33axYPENxQ2EtC8c6Nkkusjd36MQQgcM/1Z2Rh uVSXGvpgLlShzzMp4TMbZ/ITWmjwJu0ho/rGu++M= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w41EHDIW012330; Tue, 1 May 2018 09:17:13 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Tue, 1 May 2018 09:17:13 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Tue, 1 May 2018 09:17:13 -0500 Received: from [172.24.190.172] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w41EH11e011249; Tue, 1 May 2018 09:17:03 -0500 Subject: Re: [PATCH v9 06/27] ARM: davinci: da850: add new clock init using common clock framework To: David Lechner , , , CC: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Kevin Hilman , Bartosz Golaszewski , Adam Ford , References: <20180427001745.4116-1-david@lechnology.com> <20180427001745.4116-7-david@lechnology.com> From: Sekhar Nori Message-ID: <525160f1-056b-69d1-2ce2-e5bdff8bffcc@ti.com> Date: Tue, 1 May 2018 19:47:01 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20180427001745.4116-7-david@lechnology.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Friday 27 April 2018 05:47 AM, David Lechner wrote: > This adds the new board-specific clock init in mach-davinci/da850.c > using the new common clock framework drivers. > > The #ifdefs are needed to prevent compile errors until the entire > ARCH_DAVINCI is converted. > > Also clean up the #includes since we are adding some here. > > Some CFGCHIP macros were removed because we are now including > linux/mfd/da8xx-cfgchip.h which defines the same values. > > Signed-off-by: David Lechner Reviewed-by: Sekhar Nori Thanks, Sekhar