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[209.132.180.67]) by mx.google.com with ESMTP id q3-v6si9255723pgs.516.2018.05.02.00.42.34; Wed, 02 May 2018 00:42:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751492AbeEBHl5 convert rfc822-to-8bit (ORCPT + 99 others); Wed, 2 May 2018 03:41:57 -0400 Received: from mga04.intel.com ([192.55.52.120]:37584 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751436AbeEBHly (ORCPT ); Wed, 2 May 2018 03:41:54 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 May 2018 00:41:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,354,1520924400"; d="scan'208";a="50801686" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by fmsmga004.fm.intel.com with ESMTP; 02 May 2018 00:41:54 -0700 Received: from fmsmsx101.amr.corp.intel.com (10.18.124.199) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 2 May 2018 00:41:53 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx101.amr.corp.intel.com (10.18.124.199) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 2 May 2018 00:41:53 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.40]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.6]) with mapi id 14.03.0319.002; Wed, 2 May 2018 15:41:51 +0800 From: "Kang, Luwei" To: Peter Zijlstra CC: "kvm@vger.kernel.org" , "tglx@linutronix.de" , "mingo@redhat.com" , "hpa@zytor.com" , "x86@kernel.org" , "pbonzini@redhat.com" , "rkrcmar@redhat.com" , "linux-kernel@vger.kernel.org" , "joro@8bytes.org" , Chao Peng Subject: RE: [PATCH v6 01/11] perf/x86/intel/pt: Move Intel-PT MSR bit definitions to a public header Thread-Topic: [PATCH v6 01/11] perf/x86/intel/pt: Move Intel-PT MSR bit definitions to a public header Thread-Index: AQHTwLGF7CJ+ZvPIaUyuDPRh98N00qQZDtmAgAM/20A= Date: Wed, 2 May 2018 07:41:50 +0000 Message-ID: <82D7661F83C1A047AF7DC287873BF1E167F6B61D@SHSMSX101.ccr.corp.intel.com> References: <1521544918-31084-1-git-send-email-luwei.kang@intel.com> <1521544918-31084-2-git-send-email-luwei.kang@intel.com> <20180430135727.GA12258@hirez.programming.kicks-ass.net> In-Reply-To: <20180430135727.GA12258@hirez.programming.kicks-ass.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMWI0ZmMzNDEtMTgxYS00NWVjLWEzZmItNTY0ZWY5MDE2YTllIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiIraEpLeEFudCthT2lZM2hhUGdoaFNoUloyXC9QakFTTVd0WlBrMW9Oc1Vpc0xtTUpxdGo3K1dTclRsaFFWRjZ0KyJ9 dlp-product: dlpe-windows dlp-version: 11.0.200.100 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > > Intel Processor Trace virtualization enabling in guest need to use > > these MSR bits, so move them to public header msr-index.h. > > Introduce RTIT_CTL_FABRIC_EN and sync the definitions to latest spec. > > You forgot to Cc the maintainers. > > Also, this patch does 2 things, I think we have a rule that says that's a bad thing. I will split it into two patches, one patch to make these #define in a public header and another patch to add new bits for Intel Processor Trace MSRs. Thank for the review. Thanks, Luwei Kang