Received: by 10.192.165.148 with SMTP id m20csp335524imm; Wed, 2 May 2018 00:47:03 -0700 (PDT) X-Google-Smtp-Source: AB8JxZo52Z5nmUYv/OZbA71QE6H2o3MuLSrbpHhvL2bX6M3AEKD7v0ufap78kVnuXl+V96H/FX9F X-Received: by 2002:a17:902:6bc3:: with SMTP id m3-v6mr18657524plt.363.1525247222987; Wed, 02 May 2018 00:47:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525247222; cv=none; d=google.com; s=arc-20160816; b=M8aK7TdcUWQCe5mtW3+sts6zL2D4+HK2o1Xms1UZuKhnt1uvy9sfsrkGbFXgrTojYE fAbvVVB2zivoHIR8pAjHzjdMIFHkY3M+vucfWKPPwH+nyFOsYxdx5ygXbRpLLy7ROQ6q 4plBWc/W/OWg23eFkxv3pA8kTR5pG7L9cZceSN59Cz8WNQYY5/Xtl8swQE1h+G6gBZFj kPGepxPvWXchwh3YbwXiFyz3yT2P2DXmsfpMF/j5L8WZrVaRdJqEt0nWKInmNNNUPUlS L3C9wx7YLdabo+Q6rJk8i46swcNumLneIjN6wjQMd9KhasjL9z6N/7eR8rR1fmDlBmYr wk9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=0vAhWcANeLzGkWOb2HCjS/KszRdCXPqWjQ2Ha33QsAw=; b=FPvfq150QewW5QeGIe/2wBJSgEZ3VM1f0444Fydih3vxEMzBnEiUk/GQeo3qHD43lB gOsQDIcYGBvSrFeLj03Lc7MvaFiJo1jrYRv3s0N75lyjs3htT6JsggXkatZ21chGjR1/ TjnrExS5SfD4u6EDiHRiI2SrQIhM+bHWViwoRq1Ev4RmAUN4x1anR/22rgl3Z8jWqiBX jT2V/9nvyp5FHoautiIyxrKmtjM3gqII36JxECra/IFtj5b0v8iEumBhi93vOzpVuaMl eVZ2hLPSkgIY1llUf9JixZLiLfXgAXCRK9ii4nfWa5A88yJR8lttMF4qL3f0EOozx9i3 Jh0A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r22-v6si11191554pls.591.2018.05.02.00.46.49; Wed, 02 May 2018 00:47:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751472AbeEBHqH (ORCPT + 99 others); Wed, 2 May 2018 03:46:07 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:31218 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751399AbeEBHp4 (ORCPT ); Wed, 2 May 2018 03:45:56 -0400 Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w427Iv7O020745; Wed, 2 May 2018 09:45:01 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2hn55k5bp4-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Wed, 02 May 2018 09:45:01 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id BC7493D; Wed, 2 May 2018 07:45:00 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node3.st.com [10.75.127.15]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 7AF6D153B; Wed, 2 May 2018 07:45:00 +0000 (GMT) Received: from localhost (10.75.127.51) by SFHDAG5NODE3.st.com (10.75.127.15) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 2 May 2018 09:44:59 +0200 From: Fabrice Gasnier To: , , CC: , , , , , , , , , , Subject: [PATCH v2 1/3] dt-bindings: iio: stm32-adc: add support for STM32MP1 Date: Wed, 2 May 2018 09:44:49 +0200 Message-ID: <1525247091-18143-2-git-send-email-fabrice.gasnier@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1525247091-18143-1-git-send-email-fabrice.gasnier@st.com> References: <1525247091-18143-1-git-send-email-fabrice.gasnier@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.75.127.51] X-ClientProxiedBy: SFHDAG3NODE2.st.com (10.75.127.8) To SFHDAG5NODE3.st.com (10.75.127.15) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-05-02_03:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document support for STM32MP1 ADC. It's quite similar to STM32H7 ADC. Introduce "st,stm32mp1-adc" compatible to handle variants of this hardware such as vregready flag, interrupts, clock rate. Signed-off-by: Fabrice Gasnier --- Changes in v2: - Update dt-bindings following Rob's remark: STM32MP1 ADC has two interrupt lines --- Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt index e8bb824..f1ead43 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt @@ -24,8 +24,11 @@ Required properties: - compatible: Should be one of: "st,stm32f4-adc-core" "st,stm32h7-adc-core" + "st,stm32mp1-adc-core" - reg: Offset and length of the ADC block register set. -- interrupts: Must contain the interrupt for ADC block. +- interrupts: One or more interrupts for ADC block. Some parts like stm32f4 + and stm32h7 share a common ADC interrupt line. stm32mp1 has two separate + interrupt lines, one for each ADC within ADC block. - clocks: Core can use up to two clocks, depending on part used: - "adc" clock: for the analog circuitry, common to all ADCs. It's required on stm32f4. @@ -53,6 +56,7 @@ Required properties: - compatible: Should be one of: "st,stm32f4-adc" "st,stm32h7-adc" + "st,stm32mp1-adc" - reg: Offset of ADC instance in ADC block (e.g. may be 0x0, 0x100, 0x200). - clocks: Input clock private to this ADC instance. It's required only on stm32f4, that has per instance clock input for registers access. -- 1.9.1