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[209.132.180.67]) by mx.google.com with ESMTP id s2-v6si9356989pge.176.2018.05.02.03.04.28; Wed, 02 May 2018 03:04:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751840AbeEBKCf convert rfc822-to-8bit (ORCPT + 99 others); Wed, 2 May 2018 06:02:35 -0400 Received: from ZXSHCAS1.zhaoxin.com ([203.148.12.81]:21654 "EHLO ZXSHCAS1.zhaoxin.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751731AbeEBKCb (ORCPT ); Wed, 2 May 2018 06:02:31 -0400 Received: from zxbjmbx3.zhaoxin.com (10.29.252.165) by ZXSHCAS1.zhaoxin.com (10.28.252.161) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Wed, 2 May 2018 18:02:25 +0800 Received: from TIMGUOE40 (10.29.8.18) by zxbjmbx3.zhaoxin.com (10.29.252.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Wed, 2 May 2018 18:02:24 +0800 From: David Wang To: 'Borislav Petkov' CC: , , , , , , , , , , , , , Subject: Re: [PATCH v3 2/2] x86/mce: add CMCI support for Centaur CPUs Date: Wed, 2 May 2018 18:02:12 +0800 Message-ID: <000001d3e1fc$a3fd21c0$ebf76540$@zhaoxin.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdPh/HTT7L1z+0x3QWSEHUB3WrRpXA== Content-Language: zh-cn X-Originating-IP: [10.29.8.18] X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To zxbjmbx3.zhaoxin.com (10.29.252.165) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Mail----- > Sender: Borislav Petkov [mailto:bp@alien8.de] > Time: 2018年4月30日 17:48 > Receiver: David Wang > CC: tony.luck@intel.com; tglx@linutronix.de; mingo@redhat.com; > hpa@zytor.com; gregkh@linuxfoundation.org; x86@kernel.org; linux- > kernel@vger.kernel.org; linux-edac@vger.kernel.org; brucechang@via- > alliance.com; cooperyan@zhaoxin.com; qiyuanwang@zhaoxin.com; > benjaminpan@viatech.com; lukelin@viacpu.com; timguo@zhaoxin.com > Subject: Re: [PATCH v3 2/2] x86/mce: add CMCI support for Centaur CPUs > > On Wed, Apr 25, 2018 at 06:33:40PM +0800, David Wang wrote: > > Newer Centaur support CMCI mechnism, which is compatible with INTEL > CMCI. > > > > Signed-off-by: David Wang > > --- > > arch/x86/kernel/cpu/mcheck/mce.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/arch/x86/kernel/cpu/mcheck/mce.c > > b/arch/x86/kernel/cpu/mcheck/mce.c > > index 38ccab8..f9a7295 100644 > > --- a/arch/x86/kernel/cpu/mcheck/mce.c > > +++ b/arch/x86/kernel/cpu/mcheck/mce.c > > @@ -1757,6 +1757,8 @@ static void __mcheck_cpu_init_vendor(struct > cpuinfo_x86 *c) > > } > > case X86_VENDOR_CENTAUR: > > mce_centaur_feature_init(c); > > + mce_intel_feature_init(c); > > + mce_adjust_timer = cmci_intel_adjust_timer; > > This won't work in configs with CONFIG_X86_MCE_INTEL disabled. > > You need to define CONFIG_X86_MCE_CENTAUR or so which depends on > CONFIG_CPU_SUP_CENTAUR and CONFIG_X86_MCE_INTEL and which then > makes sure the intel CMCI et al stuff is enabled. > > -- > Regards/Gruss, > Boris. > > Good mailing practices for 400: avoid top-posting and trim the reply. OK. I got it. I will send another patch. Thank you. --- David