Received: by 10.192.165.148 with SMTP id m20csp614199imm; Wed, 2 May 2018 06:07:20 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpj0IncdUvq3lUgLBy+Ukbzqv//56T6P5p8AUK/ZEIkFsy5vILbRCLMnyPWpqH6Jmnn5WOT X-Received: by 2002:a65:45c6:: with SMTP id m6-v6mr16166926pgr.244.1525266440570; Wed, 02 May 2018 06:07:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525266440; cv=none; d=google.com; s=arc-20160816; b=W+2HUiNMXrycuuJVprqd8ebjuSTTDfHEwt7Sgn5K8aguSXk46c+tTmVTsT5NcPUhIB fANxetKXocmD3qJAC5K/5CT1b2XaCBgLpKus64/Ro3XKQm41rHJJGaWSYkffJDjHus/X t2qIGCKMVbzvYn2X+VxpVgEPH/2qCV0wGP9T1FPYveJPlzasRhNoVlK9ADqBPxBvXL0J wj64YurAZhsNiFkOqXxOBbfeMdBXr5HtIDAX2OLbV9VAEL9OhIkCbRWmgHTqcTtKOsrm 9ElhmxLbCaLFP1NjiI/4JecIEKe84yguhyMjIDPJA3VjXAxJ1n7Ml7INu55n3E7MJlRB vYjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=VnHdAuiRXZpAESPpLEBOyAMhtoeAjMTEOjiSS3GrFXU=; b=hg6guNwV9KcYA1vcV+rWXj1k5iDShLjye3evJsVc9myMqPnTCQP/NUjpsUITR71wRJ wcEMu4y+z8lIZkCOPl/pqXs5O34zOfALxtO1CbHnnZaQ7V1dFmriheenIWLb3oPIKtJ1 Nt2pETYkx0UZ1F5s6V6EMX5PWqMkNPYTLRhV1F2o07QlaCkmVuyAa1PcGbI/kYgKugBH O0vM9yCZYqj8GoxLVWQrEzgc01GfixEaAwpAd91FKGgN9buToV8lGwd2IUuE809xqhJc Ye4RPmW9BAkX7VMevzxeVQqt7KgaIy3K/R+5X9LEBR+fSLlekK6Y3Z8tBt5dLUA4wLbb 7EQg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f38-v6si11711107plb.44.2018.05.02.06.06.55; Wed, 02 May 2018 06:07:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751310AbeEBNGf (ORCPT + 99 others); Wed, 2 May 2018 09:06:35 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:37274 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751054AbeEBNGb (ORCPT ); Wed, 2 May 2018 09:06:31 -0400 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w42D4fAs005483; Wed, 2 May 2018 15:05:47 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2hqd1jr8g8-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Wed, 02 May 2018 15:05:46 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 101D231; Wed, 2 May 2018 13:05:44 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node3.st.com [10.75.127.15]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id B3D332AA3; Wed, 2 May 2018 13:05:44 +0000 (GMT) Received: from localhost (10.75.127.44) by SFHDAG5NODE3.st.com (10.75.127.15) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 2 May 2018 15:05:44 +0200 From: Fabrice Gasnier To: , , CC: , , , , , , , , , , , Subject: [PATCH] iio: adc: stm32-dfsdm: Add support for stm32mp1 Date: Wed, 2 May 2018 15:05:23 +0200 Message-ID: <1525266323-4922-1-git-send-email-fabrice.gasnier@st.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.75.127.44] X-ClientProxiedBy: SFHDAG1NODE1.st.com (10.75.127.1) To SFHDAG5NODE3.st.com (10.75.127.15) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-05-02_05:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for DFSDM (Digital Filter For Sigma Delta Modulators) to STM32MP1. This variant is close to STM32H7 DFSDM, it implements 6 filter instances. Registers map is also increased. Signed-off-by: Fabrice Gasnier --- .../bindings/iio/adc/st,stm32-dfsdm-adc.txt | 7 +++++-- drivers/iio/adc/stm32-dfsdm-core.c | 21 +++++++++++++++++++++ 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt index ed7520d..75ba25d 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt @@ -8,14 +8,16 @@ It is mainly targeted for: - PDM microphones (audio digital microphone) It features up to 8 serial digital interfaces (SPI or Manchester) and -up to 4 filters on stm32h7. +up to 4 filters on stm32h7 or 6 filters on stm32mp1. Each child node match with a filter instance. Contents of a STM32 DFSDM root node: ------------------------------------ Required properties: -- compatible: Should be "st,stm32h7-dfsdm". +- compatible: Should be one of: + "st,stm32h7-dfsdm" + "st,stm32mp1-dfsdm" - reg: Offset and length of the DFSDM block register set. - clocks: IP and serial interfaces clocking. Should be set according to rcc clock ID and "clock-names". @@ -45,6 +47,7 @@ Required properties: "st,stm32-dfsdm-adc" for sigma delta ADCs "st,stm32-dfsdm-dmic" for audio digital microphone. - reg: Specifies the DFSDM filter instance used. + Valid values are from 0 to 3 on stm32h7, 0 to 5 on stm32mp1. - interrupts: IRQ lines connected to each DFSDM filter instance. - st,adc-channels: List of single-ended channels muxed for this ADC. valid values: diff --git a/drivers/iio/adc/stm32-dfsdm-core.c b/drivers/iio/adc/stm32-dfsdm-core.c index e50efdc..d924e6c 100644 --- a/drivers/iio/adc/stm32-dfsdm-core.c +++ b/drivers/iio/adc/stm32-dfsdm-core.c @@ -25,6 +25,8 @@ struct stm32_dfsdm_dev_data { #define STM32H7_DFSDM_NUM_FILTERS 4 #define STM32H7_DFSDM_NUM_CHANNELS 8 +#define STM32MP1_DFSDM_NUM_FILTERS 6 +#define STM32MP1_DFSDM_NUM_CHANNELS 8 static bool stm32_dfsdm_volatile_reg(struct device *dev, unsigned int reg) { @@ -61,6 +63,21 @@ static bool stm32_dfsdm_volatile_reg(struct device *dev, unsigned int reg) .regmap_cfg = &stm32h7_dfsdm_regmap_cfg, }; +static const struct regmap_config stm32mp1_dfsdm_regmap_cfg = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = sizeof(u32), + .max_register = 0x7fc, + .volatile_reg = stm32_dfsdm_volatile_reg, + .fast_io = true, +}; + +static const struct stm32_dfsdm_dev_data stm32mp1_dfsdm_data = { + .num_filters = STM32MP1_DFSDM_NUM_FILTERS, + .num_channels = STM32MP1_DFSDM_NUM_CHANNELS, + .regmap_cfg = &stm32mp1_dfsdm_regmap_cfg, +}; + struct dfsdm_priv { struct platform_device *pdev; /* platform device */ @@ -243,6 +260,10 @@ static int stm32_dfsdm_parse_of(struct platform_device *pdev, .compatible = "st,stm32h7-dfsdm", .data = &stm32h7_dfsdm_data, }, + { + .compatible = "st,stm32mp1-dfsdm", + .data = &stm32mp1_dfsdm_data, + }, {} }; MODULE_DEVICE_TABLE(of, stm32_dfsdm_of_match); -- 1.9.1