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[209.132.180.67]) by mx.google.com with ESMTP id a2-v6si10318722pgq.278.2018.05.02.19.33.26; Wed, 02 May 2018 19:33:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752099AbeECCdB (ORCPT + 99 others); Wed, 2 May 2018 22:33:01 -0400 Received: from ZXSHCAS2.zhaoxin.com ([203.148.12.82]:8816 "EHLO ZXSHCAS2.zhaoxin.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751929AbeECCc5 (ORCPT ); Wed, 2 May 2018 22:32:57 -0400 Received: from zxbjmbx3.zhaoxin.com (10.29.252.165) by ZXSHCAS2.zhaoxin.com (10.28.252.162) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Thu, 3 May 2018 10:32:52 +0800 Received: from timguo-System-Product-Name.zhaoxin.com (10.29.8.54) by zxbjmbx3.zhaoxin.com (10.29.252.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Thu, 3 May 2018 10:32:51 +0800 From: David Wang To: , , , , , CC: , , , , , , David Wang Subject: [PATCH 2/3] x86/cpu: Include cpu_detect_cache_sizes in init_intel_cacheinfo Date: Thu, 3 May 2018 10:32:45 +0800 Message-ID: <1525314766-18910-3-git-send-email-davidwang@zhaoxin.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1525314766-18910-1-git-send-email-davidwang@zhaoxin.com> References: <1525314766-18910-1-git-send-email-davidwang@zhaoxin.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.29.8.54] X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To zxbjmbx3.zhaoxin.com (10.29.252.165) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Clean up the silly cpu_detect_cache_sizes() calling by including the cpu_detect_cache_sizes() inside the init_intel_cacheinfo(). Signed-off-by: David Wang --- arch/x86/kernel/cpu/intel.c | 8 +------- arch/x86/kernel/cpu/intel_cacheinfo.c | 6 ++++++ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index f683f7d..56e3259 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -659,13 +659,7 @@ static void init_intel(struct cpuinfo_x86 *c) #endif } - l2 = init_intel_cacheinfo(c); - - /* Detect legacy cache sizes if init_intel_cacheinfo did not */ - if (l2 == 0) { - cpu_detect_cache_sizes(c); - l2 = c->x86_cache_size; - } + init_intel_cacheinfo(c); if (c->cpuid_level > 9) { unsigned eax = cpuid_eax(10); diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index 54d04d5..2a0597c 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c @@ -20,6 +20,8 @@ #include #include +#include "cpu.h" + #define LVL_1_INST 1 #define LVL_1_DATA 2 #define LVL_2 3 @@ -802,6 +804,10 @@ unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c) c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d)); + if (!l2) { + cpu_detect_cache_sizes(c); + l2 = c->x86_cache_size; + } return l2; } -- 1.9.1