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[209.132.180.67]) by mx.google.com with ESMTP id z25-v6si6820643pgu.486.2018.05.03.00.37.12; Thu, 03 May 2018 00:37:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751011AbeECHfc convert rfc822-to-8bit (ORCPT + 99 others); Thu, 3 May 2018 03:35:32 -0400 Received: from prv1-mh.provo.novell.com ([137.65.248.33]:55241 "EHLO prv1-mh.provo.novell.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750773AbeECHfb (ORCPT ); Thu, 3 May 2018 03:35:31 -0400 Received: from INET-PRV1-MTA by prv1-mh.provo.novell.com with Novell_GroupWise; Thu, 03 May 2018 01:35:30 -0600 Message-Id: <5AEABBBF02000078001C05B0@prv1-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 18.0.0 Date: Thu, 03 May 2018 01:35:27 -0600 From: "Jan Beulich" To: "Boris Ostrovsky" Cc: "xen-devel" , "Juergen Gross" , , Subject: Re: [Xen-devel] [PATCH 3/4] xen/PVH: Set up GS segment for stack canary References: <20180430162339.17143-1-boris.ostrovsky@oracle.com> <20180430162339.17143-4-boris.ostrovsky@oracle.com> <5AE973CD02000078001C008E@prv1-mh.provo.novell.com> <615b0e30-c360-3ad4-f1b3-0e907d790643@oracle.com> <5AE9D2DD02000078001C02F0@prv1-mh.provo.novell.com> <6729d0ff-31ff-779d-6d6f-511f9ee29e50@oracle.com> <5AE9DC1D02000078001C0370@prv1-mh.provo.novell.com> <9ed1210b-47ce-7e03-cc5d-2866bfc7ad03@oracle.com> In-Reply-To: <9ed1210b-47ce-7e03-cc5d-2866bfc7ad03@oracle.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 8BIT Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org >>> On 02.05.18 at 19:29, wrote: > On 05/02/2018 11:41 AM, Jan Beulich wrote: >>>>> On 02.05.18 at 17:22, wrote: >>> On 05/02/2018 11:01 AM, Jan Beulich wrote: >>>>>>> On 02.05.18 at 17:00, wrote: >>>>> On 05/02/2018 04:16 AM, Jan Beulich wrote: >>>>>>>>> On 30.04.18 at 18:23, wrote: >>>>>>> --- a/arch/x86/xen/xen-pvh.S >>>>>>> +++ b/arch/x86/xen/xen-pvh.S >>>>>>> @@ -54,6 +54,9 @@ >>>>>>> * charge of setting up it's own stack, GDT and IDT. >>>>>>> */ >>>>>>> >>>>>>> +#define PVH_GDT_ENTRY_CANARY 4 >>>>>>> +#define PVH_CANARY_SEL (PVH_GDT_ENTRY_CANARY * 8) >>>>>> I can only advise against doing it this way: There's no safeguard against >>>>>> someone changing asm/segment.h without changing this value (in fact >>>>>> this applies to all of the GDT selectors populated in this file). At the >>>>> very >>>>>> least tie this to GDT_ENTRY_BOOT_TSS / __BOOT_TSS? >>>>>> >>>>>>> @@ -64,6 +67,9 @@ ENTRY(pvh_start_xen) >>>>>>> mov %eax,%es >>>>>>> mov %eax,%ss >>>>>>> >>>>>>> + mov $(PVH_CANARY_SEL),%eax >>>>>>> + mov %eax,%gs >>>>>>> + >>>>>>> /* Stash hvm_start_info. */ >>>>>>> mov $_pa(pvh_start_info), %edi >>>>>>> mov %ebx, %esi >>>>>>> @@ -150,6 +156,7 @@ gdt_start: >>>>>>> .quad 0x00cf9a000000ffff /* __BOOT_CS */ >>>>>>> #endif >>>>>>> .quad 0x00cf92000000ffff /* __BOOT_DS */ >>>>>>> + .quad 0x0040900000000018 /* PVH_CANARY_SEL */ >>>>>> Without any further code before loading the selector, this points at >>>>>> physical address 0. Don't you need to add in the base address of >>>>>> the per-CPU stack_canary? >>>>> This GDT is gone soon after we jump into generic x86 startup code.That >>>>> code will load its own GDT (and then set up per-cpu segments and all that). >>>> All understood, but why would you set up the per-CPU segment here if >>>> what you load into the segment register is not usable for the intended >>>> purpose (until that other code sets up things and reloads the segment >>>> registers)? >>> The intended purpose here is to allow stack protector access not to >>> fail. At this point it doesn't really matter that GS is later used for >>> per-cpu segment, this code (and this GDT) will not be used when other >>> CPUs come up. >> But the place the canary would live this way is completely wrong. > > > Would creating a canary variable and using it as a base address be better? Of course, because then at least you properly control where an eventual access would go, instead of touching some unrelated memory location. Jan