Received: by 10.192.165.148 with SMTP id m20csp1655790imm; Thu, 3 May 2018 03:16:13 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpiJWvhlS6ecBNrtfczfhUqTTQF0mxxuCX/2HDT8p4VXFIgO8UvFbGBFafOIjc0zzgA/oHX X-Received: by 2002:a63:b54b:: with SMTP id u11-v6mr18769585pgo.365.1525342573016; Thu, 03 May 2018 03:16:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525342572; cv=none; d=google.com; s=arc-20160816; b=sG7GfoxjtLTqdsJM05epNORcLExKdIYNgbpf4xFUg6XA6B9WAa2dtSKXZCd7abSMgO b1MnnXbgX7QwNWxnxd/yeN5rO+9GY/pDHFyM8wNZcK0hAgR9lEhPEJdzYDWTQpHjrQlG kHaX8iz4iRdJiBEdVnEfrM9hWrbGhtjiwJzHlJVFT1G+BJ/nNBz7HlHhAiDYQAqZbWNd AJGtUShWUKq2QfyA4KVISuWf7zort5ifwtviYmiYND6iyaEiQ1jdM5ici/UUEltt959s W/eVn3O2ENyxoDlzqQriuwDVUnUU5GpGyvMVDGYojkzwWlFR31j4Z5YUh2NCPDWljgZ6 SUMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=tSmgRRQq70QdbJi+b+iu/7vqg7Jrf0SZNe2h8WlcmNo=; b=Uoa8sVtxjP0bvOdek0eUoR+5XzcONq2FBiuYbtQZ8cjgguY9Tf3RJ8NH9qZAMSRzZS RWYcE0bvnc3IKkcaZg3a2oUFwUZtmWNZvPIVN4ga8AWfztBZapMrd/09y55tkQDINhl6 iY3IQHtyjniX9GTo3hjg18Gj3pplR6zASHEjH647RLx9ICkghw5KpsrvCmuKyjcl7jrh B38G6wHWBB5Rc49wF/NSIrU3xZKZNJlxUNG1O6f7nJmcNVVpV82jxr15XU40cFNSdpBr jvO8WQzTPyTDg15JqxuTNh4PlQmaVTDNRq2yx2e4opjQKuyHA7/t/ny3YZoTissi5wIX bk7Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c2-v6si13403981plb.77.2018.05.03.03.15.58; Thu, 03 May 2018 03:16:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752112AbeECKPH (ORCPT + 99 others); Thu, 3 May 2018 06:15:07 -0400 Received: from mga03.intel.com ([134.134.136.65]:44391 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751701AbeECKOx (ORCPT ); Thu, 3 May 2018 06:14:53 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 May 2018 03:14:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,358,1520924400"; d="scan'208";a="38109753" Received: from unknown (HELO skx-d.bj.intel.com) ([10.238.154.68]) by orsmga007.jf.intel.com with ESMTP; 03 May 2018 03:14:50 -0700 From: Luwei Kang To: kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, pbonzini@redhat.com, rkrcmar@redhat.com, linux-kernel@vger.kernel.org, joro@8bytes.org, peterz@infradead.org, chao.p.peng@linux.intel.com, Luwei Kang Subject: [PATCH v7 03/13] perf/x86/intel/pt: Add new bit definitions for Intel PT MSRs Date: Thu, 3 May 2018 20:08:33 +0800 Message-Id: <1525349323-9938-4-git-send-email-luwei.kang@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1525349323-9938-1-git-send-email-luwei.kang@intel.com> References: <1525349323-9938-1-git-send-email-luwei.kang@intel.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org These new bit definitions are use for emulate MSRs read/write for KVM. For example, IA32_RTIT_CTL.FabricEn[bit 6] is available only when CPUID.(EAX=14H, ECX=0):ECX[bit 3] = 1. If KVM guest try to set this bit with CPUID.(EAX=14H, ECX=0):ECX[bit3] = 0 a #GP would be injected to KVM guest. Signed-off-by: Luwei Kang --- arch/x86/include/asm/msr-index.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index c168e26..cc9e681 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -112,6 +112,7 @@ #define RTIT_CTL_USR BIT(3) #define RTIT_CTL_PWR_EVT_EN BIT(4) #define RTIT_CTL_FUP_ON_PTW BIT(5) +#define RTIT_CTL_FABRIC_EN BIT(6) #define RTIT_CTL_CR3EN BIT(7) #define RTIT_CTL_TOPA BIT(8) #define RTIT_CTL_MTC_EN BIT(9) @@ -140,6 +141,8 @@ #define RTIT_STATUS_BUFFOVF BIT(3) #define RTIT_STATUS_ERROR BIT(4) #define RTIT_STATUS_STOPPED BIT(5) +#define RTIT_STATUS_BYTECNT_OFFSET 32 +#define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) #define MSR_IA32_RTIT_ADDR0_A 0x00000580 #define MSR_IA32_RTIT_ADDR0_B 0x00000581 #define MSR_IA32_RTIT_ADDR1_A 0x00000582 -- 1.8.3.1