Received: by 10.192.165.148 with SMTP id m20csp1662143imm; Thu, 3 May 2018 03:23:29 -0700 (PDT) X-Google-Smtp-Source: AB8JxZp/5ArBJxiFTuYL/VS1gOAWcio3FWp3RB5GGVYfQZ1rxiOJ5enRV96TMpIvexxLPKfqB7/s X-Received: by 10.167.130.22 with SMTP id k22mr22592328pfi.73.1525343009631; Thu, 03 May 2018 03:23:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525343009; cv=none; d=google.com; s=arc-20160816; b=oWNu+TLzJ7WQT3jFMvEl4bAtC80z+VP3CA4sxNU5VjDnORfbtATFw5VRlnIiPpjrW1 5aJOsO/jf1Uel2iL0e+nMYG27Tsz5JHAIbArKZ+Ivphd2UnbCezDn99Trpnk8kazX69y 4lFgDCnWoWOYIpdUj2Pu4Qf4nxBI62eYor5JRdoZnD51gsToQYsUAQVxaMzCUDnCeABQ maMzjDtnSMAmnrz7ZgnFRF7dLK7jSJlHANQwGlx/+4J9YPSuIszBRqozsT97XDjT65vw kC+H/4mlX/ZrtUDczqEf7iFWGNZBjTKezktNI+11GV07InM2t++NJfqnJbUKdgV61Zy+ pjRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=tSmgRRQq70QdbJi+b+iu/7vqg7Jrf0SZNe2h8WlcmNo=; b=Sm+qF4fUAPrYwmtbA9Aow/O/sNQDDD9Ajq9R/Fm3VTgkkG395g42kRVW1i/UxRt0HY GTTRmuRbsYVdIfXTamsbHK9kWk1ENi7auRxYH3ksH9V6XeXRpV7Gin+KHs/kessJ4VsX DCSVwjMadA9U7HqcyJKbAG8kI5BYFx2Xm1ZLJ2vwqHnb7UcegHRf0C3wpBz/O9ufAeGQ jgQFTNtUBANCE77zWwA9/d0p3ckRZQvWgLrb6tYX8gJqg1l8sPsm0N+N/EGKpkkt7BdT ktxk+4WkMgHYU2M1+/36N3aqW0FtboEc6Jwe3/u/UmJxRdkBJpXAXNsuyD5f35qp/Dqj 4cSg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 92-v6si13185630pli.455.2018.05.03.03.23.15; Thu, 03 May 2018 03:23:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752253AbeECKWv (ORCPT + 99 others); Thu, 3 May 2018 06:22:51 -0400 Received: from mga06.intel.com ([134.134.136.31]:65500 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751593AbeECKTF (ORCPT ); Thu, 3 May 2018 06:19:05 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 May 2018 03:19:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,358,1520924400"; d="scan'208";a="36546452" Received: from unknown (HELO skx-d.bj.intel.com) ([10.238.154.68]) by fmsmga007.fm.intel.com with ESMTP; 03 May 2018 03:19:02 -0700 From: Luwei Kang To: kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, pbonzini@redhat.com, rkrcmar@redhat.com, linux-kernel@vger.kernel.org, joro@8bytes.org, peterz@infradead.org, chao.p.peng@linux.intel.com, Luwei Kang Subject: [PATCH v7 03/13] perf/x86/intel/pt: Add new bit definitions for Intel PT MSRs Date: Thu, 3 May 2018 20:13:18 +0800 Message-Id: <1525349608-10352-4-git-send-email-luwei.kang@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1525349608-10352-1-git-send-email-luwei.kang@intel.com> References: <1525349608-10352-1-git-send-email-luwei.kang@intel.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org These new bit definitions are use for emulate MSRs read/write for KVM. For example, IA32_RTIT_CTL.FabricEn[bit 6] is available only when CPUID.(EAX=14H, ECX=0):ECX[bit 3] = 1. If KVM guest try to set this bit with CPUID.(EAX=14H, ECX=0):ECX[bit3] = 0 a #GP would be injected to KVM guest. Signed-off-by: Luwei Kang --- arch/x86/include/asm/msr-index.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index c168e26..cc9e681 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -112,6 +112,7 @@ #define RTIT_CTL_USR BIT(3) #define RTIT_CTL_PWR_EVT_EN BIT(4) #define RTIT_CTL_FUP_ON_PTW BIT(5) +#define RTIT_CTL_FABRIC_EN BIT(6) #define RTIT_CTL_CR3EN BIT(7) #define RTIT_CTL_TOPA BIT(8) #define RTIT_CTL_MTC_EN BIT(9) @@ -140,6 +141,8 @@ #define RTIT_STATUS_BUFFOVF BIT(3) #define RTIT_STATUS_ERROR BIT(4) #define RTIT_STATUS_STOPPED BIT(5) +#define RTIT_STATUS_BYTECNT_OFFSET 32 +#define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) #define MSR_IA32_RTIT_ADDR0_A 0x00000580 #define MSR_IA32_RTIT_ADDR0_B 0x00000581 #define MSR_IA32_RTIT_ADDR1_A 0x00000582 -- 1.8.3.1