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[209.132.180.67]) by mx.google.com with ESMTP id k65si14024387pfg.38.2018.05.03.04.55.46; Thu, 03 May 2018 04:56:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=mLq9PS+/; dkim=pass header.i=@codeaurora.org header.s=default header.b=Zc6nrX1n; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752113AbeECLzG (ORCPT + 99 others); Thu, 3 May 2018 07:55:06 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:35356 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751268AbeECLxm (ORCPT ); Thu, 3 May 2018 07:53:42 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 6775D60C64; Thu, 3 May 2018 11:53:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1525348421; bh=VLbqP/3E9vkHtbHJyWYQBaYosRCiIadwL5aD0IK0RtQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mLq9PS+/K4mP/0x05QAxqUPN73dx1T/8Wk2jHYyhWCzIwU+6TtWkoPnitrCwUiRAE FMCPtGl2LEyooXVBtsafVYv43Qjx7p4VyGVhIiqiVRWYQMb9gkmxHjXZSTK+9303Zw PI6qpTUoHoGUfTdwgLqJQtdudjpO7UJdwUQlk+Zg= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from lx-ilial.mea.qualcomm.com (unknown [185.23.60.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilialin@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 225EE607E5; Thu, 3 May 2018 11:53:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1525348420; bh=VLbqP/3E9vkHtbHJyWYQBaYosRCiIadwL5aD0IK0RtQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Zc6nrX1nFDqeedVPvC7EbzQLLoZZsYzDASX1WXqBXPmFOaaHndo6KD/F9Y7dktBlr 5bawBYKvFA9Yq6LtOkCRdGQbWbuYRNnv/jZPaVH2Kd/G4T4RoTVBd2vFwioSrJrfsR jbjR2L3RkH4MpxIj0qIVZtoHGqg8S3uEF/uldc0I= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 225EE607E5 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilialin@codeaurora.org From: Ilia Lin To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, mark.rutland@arm.com, rjw@rjwysocki.net, viresh.kumar@linaro.org, lgirdwood@gmail.com, broonie@kernel.org, andy.gross@linaro.org, david.brown@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, rnayak@codeaurora.org, ilialin@codeaurora.org, amit.kucheria@linaro.org, nicolas.dechesne@linaro.org, celster@codeaurora.org, tfinkel@codeaurora.org Subject: [PATCH v5 10/14] dt-bindings: qcom_spmi: Add support for SAW documentation Date: Thu, 3 May 2018 14:52:31 +0300 Message-Id: <1525348355-25471-11-git-send-email-ilialin@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1525348355-25471-1-git-send-email-ilialin@codeaurora.org> References: <1525348355-25471-1-git-send-email-ilialin@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for SAW controlled regulators. The regulators defined as SAW controlled in the device tree will be controlled through special CPU registers instead of direct SPMI accesses. This is required especially for CPU supply regulators to synchronize with clock scaling and for Automatic Voltage Switching. Document it. Signed-off-by: Ilia Lin --- .../bindings/regulator/qcom,spmi-regulator.txt | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt b/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt index 57d2c65..406f2e5 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt @@ -110,6 +110,11 @@ Qualcomm SPMI Regulators Definition: Reference to regulator supplying the input pin, as described in the data sheet. +- qcom,saw-reg: + Usage: optional + Value type: + Description: Reference to syscon node defining the SAW registers. + The regulator node houses sub-nodes for each regulator within the device. Each sub-node is identified using the node's name, with valid values listed for each @@ -201,6 +206,17 @@ see regulator.txt - with additional custom properties described below: 2 = 0.55 uA 3 = 0.75 uA +- qcom,saw-slave: + Usage: optional + Value type: + Description: SAW controlled gang slave. Will not be configured. + +- qcom,saw-leader: + Usage: optional + Value type: + Description: SAW controlled gang leader. Will be configured as + SAW regulator. + Example: regulators { @@ -221,3 +237,32 @@ Example: .... }; + +Example 2: + + saw3: syscon@9A10000 { + compatible = "syscon"; + reg = <0x9A10000 0x1000>; + }; + + ... + + spm-regulators { + compatible = "qcom,pm8994-regulators"; + qcom,saw-reg = <&saw3>; + s8 { + qcom,saw-slave; + }; + s9 { + qcom,saw-slave; + }; + s10 { + qcom,saw-slave; + }; + pm8994_s11_saw: s11 { + qcom,saw-leader; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1140000>; + }; + }; -- 1.9.1