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[209.132.180.67]) by mx.google.com with ESMTP id q1-v6si5207152pgc.265.2018.05.03.10.44.19; Thu, 03 May 2018 10:44:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cdDwptNI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751302AbeECRnB (ORCPT + 99 others); Thu, 3 May 2018 13:43:01 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:53691 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751007AbeECRm6 (ORCPT ); Thu, 3 May 2018 13:42:58 -0400 Received: by mail-wm0-f66.google.com with SMTP id a67so280740wmf.3 for ; Thu, 03 May 2018 10:42:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=J8LOxj3cLmUyGFpmmeWPTBz7n5JoN5/JBjdy97qVhKo=; b=cdDwptNI13ha2aGAiSYVC/IsILIx+wKDJmBAwGv7JvEsjUqLY79Tq6l5qfABzs4k7U gVxSQakWvMr4ck/k2HOAtgxRf+d3O3OAjXSbGLr4Z3mhpKoWoOfS7ni0V7aG3LJ7mNoG OZuXBiQz/yKZVQoGEk40FeBi6SRgetGOhcGKk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=J8LOxj3cLmUyGFpmmeWPTBz7n5JoN5/JBjdy97qVhKo=; b=eE2F7QUh38nCjpi5ZrfFj+Yn7++c/m1hC190HYDwdX23+E78a3ROYDyAYUUd/IRn6h yF7ibecczjzHVxsFmQ5vKV3NtkndqEa043SOvl01mXpMorUUUfAAmA9jvuf+vwHmM3I7 /Gp4Cd8mCKDszD+WLy5nGwMRVH1YSA6Zdh1hVw5vELasEetH4LQeg+OTAVRQGnYyxakb +KwwmDdj4E3ueCRFk6TZQzql/G6DX25NroGFoyKFtzcRIAMerXNbkaKC7pD0Kp8BDVCV cCDKLNg5BImIgUk1X+FRwWfZ2BR+4gtbJqKwE324gM25s1Pju0Zd+YiF9y2tM3i2h2ZO llUA== X-Gm-Message-State: ALQs6tApc1VqFbNiABNh+/HRWLCE1oF1fprX6gLP/rLA2fFPL54moBH5 YDSq0t+NWCuQ9nGnZsw73b7s6LtmAYSxc5dWNy0tCg== X-Received: by 2002:a50:b36a:: with SMTP id r39-v6mr32899271edd.145.1525369377114; Thu, 03 May 2018 10:42:57 -0700 (PDT) MIME-Version: 1.0 Received: by 10.80.164.161 with HTTP; Thu, 3 May 2018 10:42:56 -0700 (PDT) In-Reply-To: <20180501131057.GA15706@rob-hp-laptop> References: <1525165857-11096-1-git-send-email-suzuki.poulose@arm.com> <1525165857-11096-6-git-send-email-suzuki.poulose@arm.com> <20180501131057.GA15706@rob-hp-laptop> From: Mathieu Poirier Date: Thu, 3 May 2018 11:42:56 -0600 Message-ID: Subject: Re: [PATCH v2 05/27] dts: bindings: Document device tree binding for CATU To: Rob Herring Cc: Suzuki K Poulose , linux-arm-kernel , linux-kernel@vger.kernel.org, Mike Leach , Robert Walker , Mark Rutland , Will Deacon , Robin Murphy , Sudeep Holla , Frank Rowand , John Horley , devicetree@vger.kernel.org, Mathieu Poirier Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 1 May 2018 at 07:10, Rob Herring wrote: > On Tue, May 01, 2018 at 10:10:35AM +0100, Suzuki K Poulose wrote: >> Document CATU device-tree bindings. CATU augments the TMC-ETR >> by providing an improved Scatter Gather mechanism for streaming >> trace data to non-contiguous system RAM pages. >> >> Cc: devicetree@vger.kernel.org >> Cc: frowand.list@gmail.com >> Cc: Rob Herring >> Cc: Mark Rutland >> Cc: Mathieu Poirier >> Signed-off-by: Suzuki K Poulose >> --- >> .../devicetree/bindings/arm/coresight.txt | 52 ++++++++++++++++++++++ >> 1 file changed, 52 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt >> index 15ac8e8..cdd84d0 100644 >> --- a/Documentation/devicetree/bindings/arm/coresight.txt >> +++ b/Documentation/devicetree/bindings/arm/coresight.txt >> @@ -39,6 +39,8 @@ its hardware characteristcs. >> >> - System Trace Macrocell: >> "arm,coresight-stm", "arm,primecell"; [1] >> + - Coresight Address Translation Unit (CATU) >> + "arm, coresight-catu", "arm,primecell"; > > spurious space ^ > >> >> * reg: physical base address and length of the register >> set(s) of the component. >> @@ -86,6 +88,9 @@ its hardware characteristcs. >> * arm,buffer-size: size of contiguous buffer space for TMC ETR >> (embedded trace router) >> >> +* Optional property for CATU : >> + * interrupts : Exactly one SPI may be listed for reporting the address >> + error > > Somewhere you need to define the ports for the CATU. > >> >> Example: >> >> @@ -118,6 +123,35 @@ Example: >> }; >> }; >> >> + etr@20070000 { >> + compatible = "arm,coresight-tmc", "arm,primecell"; >> + reg = <0 0x20070000 0 0x1000>; >> + >> + clocks = <&oscclk6a>; >> + clock-names = "apb_pclk"; >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + /* input port */ >> + port@0 { >> + reg = <0>; >> + etr_in_port: endpoint { >> + slave-mode; >> + remote-endpoint = <&replicator2_out_port0>; >> + }; >> + }; >> + >> + /* CATU link represented by output port */ >> + port@1 { >> + reg = <0>; > > While common in the Coresight bindings, having unit-address and reg not > match is an error. Mathieu and I discussed this a bit as dtc now warns > on these. > > Either reg should be 1 here, or 'ports' needs to be split into input and > output ports. My preference would be the former, but Mathieu objected to > this not reflecting the the h/w numbering. Suzuki, as we discuss this is related to your work on revamping CS bindings for ACPI. Until that gets done and to move forward with this set I suggest you abide to Rob's request. > > Rob