Received: by 10.192.165.148 with SMTP id m20csp380939imm; Thu, 3 May 2018 22:49:26 -0700 (PDT) X-Google-Smtp-Source: AB8JxZoUPU0IgzsH8lWU0z19WD720PEYXXPB8z1TXPF+zhDBIdsboLvF3ZxSgLLXK8mDpWNMo8N9 X-Received: by 2002:a63:6d8b:: with SMTP id i133-v6mr21467030pgc.268.1525412966336; Thu, 03 May 2018 22:49:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525412966; cv=none; d=google.com; s=arc-20160816; b=E+AEsealz/Q8NcumiZtZn1MLIO6UwDj6efqzMSrRtyy0VudHRsY/Npjk4Tg36G7XxI +kuKpROSs0LhsiDhQqc09YaTCGc/8QurBHKWcrhiAYVmge3ZL0fD3SZG9bSDZrkrDswJ hKfOycTaifjuiBk3G5xDldCAVmiPfoYM2C8aZcgxY3Hdon1SDCpFtf6L897WECpW0vVs LWDYjkEi7WgXL1S4B4dV69YL0f7EbfmxQzA/NQJxnxjyYGQxgQ0hJFoDakQLHEB4DIib 5qzqogpxhrnNqAEdlE5PVOYeOCQ8axRA5Bb4tikHDRImctK/uWxSOZS4L3csg6VmquX6 Tw3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=/QFedAzeZvNKewUn1ifTn87D2IfuSeF0nVQQi1Ff6+Q=; b=bNij0Ei/wTVfsfdSH3wWGhBCIwwnpODPSwfD5WfQhirqWSesZFnV83d00w/GoC7P+d oKITTO8sEw5X1DJf6LUNs9d0xIlOjJPTSHQFuB6/2h4QUZvXWUmTLAm6xQ+ofRTIFcZR mbTSYLgwl6S7LhmnxgYRbt0yQf5mIn8Ou4p3m8lwc/jdK24XMui4kGZhZxAt7YuADOfu GIYoSJvfrNjN4o64i0booDPveL2o75IhIUFhb2CKgT/ppG3lFOY1OUmB9rA2N9GojATJ tsd/1eDeL1K628LrpctNsY37WBRkaJ5Rh9i4eb2A3cK5pOl3jjyb2Pju9UQ6PB1YwxbG PT8Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a12-v6si15146715plp.225.2018.05.03.22.49.12; Thu, 03 May 2018 22:49:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751316AbeEDFrr (ORCPT + 99 others); Fri, 4 May 2018 01:47:47 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:34641 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1750866AbeEDFro (ORCPT ); Fri, 4 May 2018 01:47:44 -0400 X-UUID: 4ef40a74ea624111813e087d1d58fb01-20180504 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1969992991; Fri, 04 May 2018 13:47:39 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Fri, 4 May 2018 13:47:37 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Fri, 4 May 2018 13:47:36 +0800 From: To: , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v7 1/2] PCI: mediatek: Set up vendor ID and class type for MT7622 Date: Fri, 4 May 2018 13:47:32 +0800 Message-ID: <1525412853-24367-2-git-send-email-honghui.zhang@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1525412853-24367-1-git-send-email-honghui.zhang@mediatek.com> References: <1525412853-24367-1-git-send-email-honghui.zhang@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Honghui Zhang MT7622's hardware default value of vendor ID and class type is not correct, fix that by setup the correct values before linkup with Endpoint. Signed-off-by: Honghui Zhang Acked-by: Ryder Lee --- drivers/pci/host/pcie-mediatek.c | 30 +++++++++++++++++++++++++++--- include/linux/pci_ids.h | 2 ++ 2 files changed, 29 insertions(+), 3 deletions(-) diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c index a8b20c5..c3dc549 100644 --- a/drivers/pci/host/pcie-mediatek.c +++ b/drivers/pci/host/pcie-mediatek.c @@ -66,6 +66,10 @@ /* PCIe V2 per-port registers */ #define PCIE_MSI_VECTOR 0x0c0 + +#define PCIE_CONF_VEND_ID 0x100 +#define PCIE_CONF_CLASS_ID 0x106 + #define PCIE_INT_MASK 0x420 #define INTX_MASK GENMASK(19, 16) #define INTX_SHIFT 16 @@ -125,12 +129,14 @@ struct mtk_pcie_port; /** * struct mtk_pcie_soc - differentiate between host generations + * @need_fix_class_id: whether this host's class ID needed to be fixed or not * @has_msi: whether this host supports MSI interrupts or not * @ops: pointer to configuration access functions * @startup: pointer to controller setting functions * @setup_irq: pointer to initialize IRQ functions */ struct mtk_pcie_soc { + bool need_fix_class_id; bool has_msi; struct pci_ops *ops; int (*startup)(struct mtk_pcie_port *port); @@ -375,6 +381,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) { struct mtk_pcie *pcie = port->pcie; struct resource *mem = &pcie->mem; + const struct mtk_pcie_soc *soc = port->pcie->soc; u32 val; size_t size; int err; @@ -403,6 +410,15 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) PCIE_MAC_SRSTB | PCIE_CRSTB; writel(val, port->base + PCIE_RST_CTRL); + /* Set up vendor ID and class code */ + if (soc->need_fix_class_id) { + val = PCI_VENDOR_ID_MEDIATEK; + writew(val, port->base + PCIE_CONF_VEND_ID); + + val = PCI_CLASS_BRIDGE_HOST; + writew(val, port->base + PCIE_CONF_CLASS_ID); + } + /* 100ms timeout value should be enough for Gen1/2 training */ err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val, !!(val & PCIE_PORT_LINKUP_V2), 20, @@ -1142,7 +1158,15 @@ static const struct mtk_pcie_soc mtk_pcie_soc_v1 = { .startup = mtk_pcie_startup_port, }; -static const struct mtk_pcie_soc mtk_pcie_soc_v2 = { +static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = { + .has_msi = true, + .ops = &mtk_pcie_ops_v2, + .startup = mtk_pcie_startup_port_v2, + .setup_irq = mtk_pcie_setup_irq, +}; + +static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = { + .need_fix_class_id = true, .has_msi = true, .ops = &mtk_pcie_ops_v2, .startup = mtk_pcie_startup_port_v2, @@ -1152,8 +1176,8 @@ static const struct mtk_pcie_soc mtk_pcie_soc_v2 = { static const struct of_device_id mtk_pcie_ids[] = { { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 }, { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 }, - { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_v2 }, - { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_v2 }, + { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 }, + { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 }, {}, }; diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index a6b3066..9d4fca5 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2115,6 +2115,8 @@ #define PCI_VENDOR_ID_MYRICOM 0x14c1 +#define PCI_VENDOR_ID_MEDIATEK 0x14c3 + #define PCI_VENDOR_ID_TITAN 0x14D2 #define PCI_DEVICE_ID_TITAN_010L 0x8001 #define PCI_DEVICE_ID_TITAN_100L 0x8010 -- 2.6.4