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[209.132.180.67]) by mx.google.com with ESMTP id y9-v6si12393093pgv.452.2018.05.03.22.59.24; Thu, 03 May 2018 22:59:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=MhsSQg/s; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751287AbeEDF7L (ORCPT + 99 others); Fri, 4 May 2018 01:59:11 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:38138 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751059AbeEDF7J (ORCPT ); Fri, 4 May 2018 01:59:09 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w445x22G013065; Fri, 4 May 2018 00:59:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1525413542; bh=4tV+dPs6ua5gmP81Tht1R6QL68ZtvsetItPvC04zce4=; h=Subject:To:References:CC:From:Date:In-Reply-To; b=MhsSQg/scIzJ00eV/c6r2n4MPxpLTwWdFatScirahaYbsT9Of6BZH54k6JBpP7aCX UZq9MsAIlXYcRn3EqRdA9U+V7Lh5r9WTH+CIOqbnZDCdcFwq73OhrUDuY/7GzFiT6Y /6K2GRrjLqEnBeLZeB7XnTcNQF7v7TvTRQ0reLgI= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w445x2VN016788; Fri, 4 May 2018 00:59:02 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 4 May 2018 00:59:02 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 4 May 2018 00:59:02 -0500 Received: from [172.24.190.233] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w445wwns020308; Fri, 4 May 2018 00:58:59 -0500 Subject: Re: [PATCH v7 3/9] PCI: endpoint: functions/pci-epf-test: Add second entry To: Lorenzo Pieralisi References: <20180426165605.GA6370@e107981-ln.cambridge.arm.com> <20180501115417.GD19391@e107981-ln.cambridge.arm.com> <5d625d04-38fe-7d5a-67fc-5ea92039474c@ti.com> <20180501142607.GA21911@e107981-ln.cambridge.arm.com> <20180502165144.GB4871@e107981-ln.cambridge.arm.com> <20180503141636.GA23270@e107981-ln.cambridge.arm.com> CC: Gustavo Pimentel , "bhelgaas@google.com" , "Joao.Pinto@synopsys.com" , "jingoohan1@gmail.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" From: Kishon Vijay Abraham I Message-ID: Date: Fri, 4 May 2018 11:28:58 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: <20180503141636.GA23270@e107981-ln.cambridge.arm.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Lorenzo, On Thursday 03 May 2018 07:46 PM, Lorenzo Pieralisi wrote: > On Thu, May 03, 2018 at 12:03:15PM +0530, Kishon Vijay Abraham I wrote: > > [...] > >>>> Since the linkup notifier and BAR index (where auxiliary registers are >>>> located) may be configurable and is something platform dependent, >>>> perhaps the configuration of this variables should be done by module >>>> parameter and not by configfs, leaving this configuration >>>> responsibility in charge of each platform. >>> >>> They are platform dependent because they depend on the EP controller. >>> That's why I said that those are EP controller parameters. I do not >>> think they are module parameters either - they should be part of HW >>> description in firmware. >> >> The problem is because pci-epf-test cannot be described in HW. pci-epf-test is >> also not automatically bound to the EP controller but is bound by the user like >> below >> ln -s functions/pci_epf_test/func1 controllers/51000000.pcie_ep/ >> >> So given that user anyways has to bind the epf device to the controller, based >> on the platform the user can use a different configfs entry like below >> ln -s functions/pci_epf_test_dw/func1 controllers/51000000.pcie_ep/ or >> ln -s functions/pci_epf_test_k2g/func1 controllers/21800000.pcie-ep/ >> >> If the epf can be described in dt, then something like below can be done >> pcie1_ep: pcie_ep@51000000 { >> compatible = "ti,dra7-pcie-ep"; >> interrupts = <0 232 0x4>; >> num-lanes = <1>; >> num-ib-windows = <4>; >> num-ob-windows = <16>; >> phys = <&pcie1_phy>; >> phy-names = "pcie-phy0"; >> pci_epf_test: pci_epf_test@0 { >> name = "pci_epf_test_dw"; >> ; >> } >> }; >> >> With this pci-dra7xx.c driver should create pci_epf_device using >> pci_epf_create("pci_epf_test_dw"); >> >> Then the driver_data corresponding to "pci_epf_test_dw" will select linkup >> notifier or BAR index etc. > > Those two properties are properties of the EP controller (it is not 100% > clear to me how the test BAR register is defined), is this correct ? Right, these properties are specific to a platform. In some of the platforms like K2G (BAR0 is reserved i.e it is used to map PCIe app registers and cannot be used by pci_epf_test. In such cases we should use a BAR other than BAR0). > > If yes, given that those properties are not useful before an EPF is > bound to an EPC, can't they be retrieved at bind time from the EPC > controller data (that we can add through DT bindings) ? hmm.. We can have quirk in pci_epc, something like below struct pci_epc { . . unsigned int quirks; . . }; #define EPC_QUIRKS_NO_LINKUP_NOTIFIER BIT(0) #define EPC_QUIRKS_BAR0_RESERVED BIT(1) #define EPC_QUIRKS_BAR1_RESERVED BIT(2) #define EPC_QUIRKS_BAR2_RESERVED BIT(3) #define EPC_QUIRKS_BAR3_RESERVED BIT(4) #define EPC_QUIRKS_BAR4_RESERVED BIT(5) #define EPC_QUIRKS_BAR5_RESERVED BIT(6) The controller driver can set the appropriate quirks epc->quirks |= EPC_QUIRKS_NO_LINKUP_NOTIFIER | EPC_QUIRKS_BAR0_RESERVED; Then pci-epf-test driver can checks the quirks to see the supported EPC features. Does something like above looks okay to you? Thanks Kishon