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[209.132.180.67]) by mx.google.com with ESMTP id a14-v6si16546120plt.484.2018.05.04.12.47.36; Fri, 04 May 2018 12:47:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@google.com header.s=20161025 header.b=vWC1sIzX; dkim=fail header.i=@chromium.org header.s=google header.b=Wh/kl00n; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751709AbeEDTrJ (ORCPT + 99 others); Fri, 4 May 2018 15:47:09 -0400 Received: from mail-ua0-f194.google.com ([209.85.217.194]:45854 "EHLO mail-ua0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751477AbeEDTrD (ORCPT ); Fri, 4 May 2018 15:47:03 -0400 Received: by mail-ua0-f194.google.com with SMTP id j5so14772588uak.12 for ; Fri, 04 May 2018 12:47:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=TxY2NRJFNja9fgJ8iHHewGcJrsDUR00y/2YDQ06XcPM=; b=vWC1sIzXpN3Ve5DHLcZ0YejHA2w6muYXbVRNrY3LCezgAnEcnmLuH9XKpflcN0qOwZ PPLMX4rz1xsOUY1+Jb3ZB4hfJutePV01+gohHfGysRDGCMVXssDbgjgLg697qR02kMjp MZ6OfGo1FPGnbjVunlS/zqEEurwDPLo9fQp7U9taGkE+sbStAKozqhvq+Zc60N2EP+2N Suchev6B/s3JJyZS2QMqwVsTpk+nCnVx0bMaYEDsRGiSiKnlpjpVMoyKy5qhmaKDQ04w mXXSqfbexgR+VDBylq4K1paMc8tNJ/5YrtPR2ZotK3aiD3xDQWW4zGUoYIGljghFGgTw S6aQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=TxY2NRJFNja9fgJ8iHHewGcJrsDUR00y/2YDQ06XcPM=; b=Wh/kl00na5JJq8sG0iWIukH7EwlEUkYIqMXmYID4NjSZMX1aJfcaB6QAodCj1yu/Eq z9zyt30nxdS/Yl6A8Wz9lHZ6Hxb4987l5sojtlyiZ2YwWBX+zfmklw/JI9jpfo7PMNaK tOlHYQ0T6FJFmRWhaYX0aVYXfXdCF/yKkqYlw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=TxY2NRJFNja9fgJ8iHHewGcJrsDUR00y/2YDQ06XcPM=; b=Lp8kwj5jdLStDvzATixp/EW8qCGpNyFY9s0wN3cQYvbPfN72ILA3/+ZbzO+JVXSHZW dvK+N9aXWjnDEmEmuxLF58WuB89/MvzUJ+gWiMEKAwM5tS2+JIkWBhIoh7u19Kgk6U8u usgRXVRRqIQLuo+rbUewItqJyXkyW2XQv63sRzctTd4Q5dSdee3onWQ2gRO/AjVmrxq+ 1HDDn6uN+eNkYcQBUk+f6/NCEhoH+zaCtBVZYoPzoefqm0hnxTU1pcTAH0JAKBG6I2Y+ BT3YHjaetggmSV1xJkUkfi4kyhHClxhH3heJ1iz0qbB3qfR3vELiJYTVjHH+SW7g7X/B Dtfg== X-Gm-Message-State: ALQs6tCPCtT9AkbWSg9OPvN71VRkbwI+RZDOA3suOkjmXVySjs60UUFX +eEMBx0O+jh2Yl6n+ULM/ILaD93ES+OAA7fLHkICFQ== X-Received: by 10.159.51.227 with SMTP id y35mr24358844uab.121.1525463222104; Fri, 04 May 2018 12:47:02 -0700 (PDT) MIME-Version: 1.0 Received: by 10.31.48.82 with HTTP; Fri, 4 May 2018 12:47:01 -0700 (PDT) In-Reply-To: <1525295174-15995-3-git-send-email-mgautam@codeaurora.org> References: <1525295174-15995-1-git-send-email-mgautam@codeaurora.org> <1525295174-15995-3-git-send-email-mgautam@codeaurora.org> From: Doug Anderson Date: Fri, 4 May 2018 12:47:01 -0700 X-Google-Sender-Auth: EY36YWTa6caiiaO2M4tInvKwTb4 Message-ID: Subject: Re: [PATCH v5 2/7] phy: qcom-qmp: Enable pipe_clk before PHY initialization To: Manu Gautam Cc: Kishon Vijay Abraham I , Rob Herring , Stephen Boyd , devicetree@vger.kernel.org, LKML , Evan Green , Vivek Gautam , linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Wed, May 2, 2018 at 2:06 PM, Manu Gautam wrote: > QMP PHY for USB/PCIE requires pipe_clk for locking of > retime buffers at the pipe interface. Driver checks for > PHY_STATUS without enabling pipe_clk due to which > phy_init() fails with initialization timeout. > Though pipe_clk is output from PHY (after PLL is programmed > during initialization sequence) to GCC clock_ctl and then fed > back to PHY but for PHY_STATUS register to reflect successful > initialization pipe_clk from GCC must be present. > Since, clock driver now ignores status_check for pipe_clk on > clk_enable/disable, driver can safely enable/disable pipe_clk > from phy_init/exit. > > Signed-off-by: Manu Gautam > --- > drivers/phy/qualcomm/phy-qcom-qmp.c | 22 ++++++++-------------- > 1 file changed, 8 insertions(+), 14 deletions(-) Given the agreement with Stephen Boyd that we'll just BRANCH_HALT_SKIP for now, this all looks good to me. Reviewed-by: Douglas Anderson