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To: Borislav Petkov Cc: Linus Torvalds , "Kirill A. Shutemov" , Linux Kernel Mailing List , Thomas Gleixner Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 2018-05-04 18:18 GMT+02:00 Borislav Petkov : > On Wed, May 02, 2018 at 02:20:52PM +0200, Thomas Gleixner wrote: >> Thanks for confirming. Still need to find a way which is less fragile, b= ut >> that's probably too much of churn for rc4.... >> >> At least I know exactly what's happening, so I can write a better change= log. >> >> Thanks for testing! > > J=C3=B6rg, can you pls also test this one ontop of Thomas' patch to make > sure it doesn't break your box. > > Thx. > > --- > From 6857c2ac8e31f4f9b350cfad4f6b6eb831bf57f1 Mon Sep 17 00:00:00 2001 > From: Borislav Petkov > Date: Wed, 2 May 2018 18:15:14 +0200 > Subject: [PATCH] x86/CPU: Use synthetic bits for IBRS/IBPB/STIBP > > Intel and AMD have different CPUID bits for those so use synthetic bits > which get set on the respective vendor in init_speculation_control(). So > that debacles like the commit message of > > c65732e4f721 ("x86/cpu: Restore CPUID_8000_0008_EBX reload") > Patch doesn't hurt me. For me it=C2=B4s ok. Thanks, J=C3=B6rg