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[209.132.180.67]) by mx.google.com with ESMTP id f142-v6si10112256iof.216.2018.05.07.08.57.59; Mon, 07 May 2018 08:58:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@google.com header.s=20161025 header.b=XmvMAdfM; dkim=fail header.i=@chromium.org header.s=google header.b=TEpk+5xS; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752774AbeEGP5b (ORCPT + 99 others); Mon, 7 May 2018 11:57:31 -0400 Received: from mail-ua0-f193.google.com ([209.85.217.193]:35220 "EHLO mail-ua0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752303AbeEGP52 (ORCPT ); Mon, 7 May 2018 11:57:28 -0400 Received: by mail-ua0-f193.google.com with SMTP id a2so18234349uak.2 for ; Mon, 07 May 2018 08:57:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=LhUNLIRoPAH+px6TAlYdiGXWdB/lWilNVyzjv05U+ho=; b=XmvMAdfMABBXxI4osbpG6eDex7wG9H0Rsgv81qze7/kVtwX/kheksjuSaI1CkgJsSx JitBIyIXKXkAi9jH6A+xbJpDSjaoQpBClpTERajQve5whsgHzFrYhvxV9MjBo6+1MJ1T BgHaP3xsU+cXvSQ39U/TahxmSqEI/EJqWgtzXU18uMEfg3yWaeQFYYMZOaGz1aX3CwI7 j3j90u0a9jNaChoB+9pNiUFZsWOYpAEUmkoVSXwvGFiCuzakdx/2yuKmFkeA17lsHt3A 1T7TZEOBfKPEUADHhYS04TEGv/hm2Ll1kFEtzYEc0KNm+mw6r7XLIiabJHvGO5p13UO8 pLlA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=LhUNLIRoPAH+px6TAlYdiGXWdB/lWilNVyzjv05U+ho=; b=TEpk+5xSIA5AZ9Ld/YfOpexPbCeeidTD/oVUbG4P0+GcbtL6JqtE+hbh4YnaiEKbhb 7XVNPMVC3wXchp44Ug2+V1nxbY4Ierw3ft820Mgy7TVD5UuyeWnjI0GdDKwtQuf3UW4e DaI7Bzf828XEH1cZ+P36dWIUNMwb3cA57OnS4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=LhUNLIRoPAH+px6TAlYdiGXWdB/lWilNVyzjv05U+ho=; b=tTJ+74Z7mZhLs+9IFlZECHPpamX/iBr8ZzV2zJG12TBWIJexIawJrot3uoRmXHGMND SOJi/tqm0RLajnv48Rd7HFYUWZ6GkGFzOK49Xd5iUlQDd3MK7RIBR2nAlDsIDouTIgIE CRpifNbqfSoCB1KvHWTOuMM+hcrBdpe9JGYEO2Dsbg4LJ7IDK4+4p/o2Q2ZRcq5CEcpv 2isg2fxpmhgcDsBVy13qN0HtEMT2iilSZJigBGBgxd0rWk7V1r+1K9kptTXlbQ9FZv2W myer6z4mr4CNk2gW43ZD6J/Gq89rIfK70K/BChuaVKZknUKXhLypRsKBJtqPhSoYQQT8 yigA== X-Gm-Message-State: ALQs6tDV8XxYgId34RnMSAO90CG6Yy07JBsEFWrIOXFPhQ5CxK6DLqnA ggCYTh2yuuXjuIpDZeZJyvxoR6joDrGs++jhtDmKNQ== X-Received: by 10.176.73.135 with SMTP id e7mr32265563uad.20.1525708647286; Mon, 07 May 2018 08:57:27 -0700 (PDT) MIME-Version: 1.0 Received: by 10.31.48.82 with HTTP; Mon, 7 May 2018 08:57:26 -0700 (PDT) In-Reply-To: <20180507155313.GA9696@rob-hp-laptop> References: <1525295174-15995-1-git-send-email-mgautam@codeaurora.org> <1525295174-15995-7-git-send-email-mgautam@codeaurora.org> <20180507155313.GA9696@rob-hp-laptop> From: Doug Anderson Date: Mon, 7 May 2018 08:57:26 -0700 X-Google-Sender-Auth: 3ku2GuKdfVz8CLzzJYExq62NTTI Message-ID: Subject: Re: [PATCH v5 6/7] dt-bindings: phy-qcom-usb2: Add support to override tuning values To: Rob Herring Cc: Manu Gautam , Kishon Vijay Abraham I , Stephen Boyd , devicetree@vger.kernel.org, LKML , Evan Green , Vivek Gautam , linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Rob, On Mon, May 7, 2018 at 8:53 AM, Rob Herring wrote: > On Thu, May 03, 2018 at 02:36:13AM +0530, Manu Gautam wrote: >> To improve eye diagram for PHYs on different boards of same SOC, >> some parameters may need to be changed. Provide device tree >> properties to override these from board specific device tree >> files. While at it, replace "qcom,qusb2-v2-phy" with compatible >> string for USB2 PHY on sdm845 which was earlier added for >> sdm845 only. >> >> Signed-off-by: Manu Gautam >> --- >> .../devicetree/bindings/phy/qcom-qusb2-phy.txt | 23 +++++++++++++- >> include/dt-bindings/phy/phy-qcom-qusb2.h | 37 ++++++++++++++++++++++ >> 2 files changed, 59 insertions(+), 1 deletion(-) >> create mode 100644 include/dt-bindings/phy/phy-qcom-qusb2.h >> >> diff --git a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt >> index 42c9742..03025d9 100644 >> --- a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt >> +++ b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt >> @@ -6,7 +6,7 @@ QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets. >> Required properties: >> - compatible: compatible list, contains >> "qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996, >> - "qcom,qusb2-v2-phy" for QUSB2 V2 PHY. >> + "qcom,sdm845-qusb2-phy" for 10nm PHY on sdm845. >> >> - reg: offset and length of the PHY register set. >> - #phy-cells: must be 0. >> @@ -27,6 +27,27 @@ Optional properties: >> tuning parameter value for qusb2 phy. >> >> - qcom,tcsr-syscon: Phandle to TCSR syscon register region. >> + - qcom,imp-res-offset-value: It is a 6 bit value that specifies offset to be >> + added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY >> + tuning parameter that may vary for different boards of same SOC. >> + This property is applicable to only QUSB2 v2 PHY (sdm845). >> + - qcom,hstx-trim-value: It is a 4 bit value that specifies tuning for HSTX >> + output current. >> + Possible range is - 15mA to 24mA (stepsize of 600 uA). >> + See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. >> + This property is applicable to only QUSB2 v2 PHY (sdm845). >> + Default value is 22.2mA for sdm845. >> + - qcom,preemphasis-level: It is a 2 bit value that specifies pre-emphasis level. >> + Possible range is 0 to 15% (stepsize of 5%). >> + See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. >> + This property is applicable to only QUSB2 v2 PHY (sdm845). >> + Default value is 10% for sdm845. >> +- qcom,preemphasis-width: It is a 1 bit value that specifies how long the HSTX >> + pre-emphasis (specified using qcom,preemphasis-level) must be in >> + effect. Duration could be half-bit of full-bit. > > s/of/or/ > > But I'd just make this a boolean instead: qcom,preemphasis-half-bit I had this same comment in the post of v4. See . Specifically, I said: > Perhaps just make this a boolean property. If it exists then you get > the non-default case. AKA: if the default is full bit width, then > you'd allow a boolean property "qcom,preemphasis-half-width" to > override. If the default is half bit width then you'd allow > "qcom,preemphasis-full-width" to override. Manu replied: > Default property value for an SOC is specified in driver and could vary from > soc to soc. Hence, from board devicetree for different SOCs we might need > to select separate widths overriding default driver values. > Alternative is to have two bool properties each for half and full-width. Did > you actually mean that? IMHO given Manu's argument it seems fine to specify it the way he did. Please advise if you agree or disagree. -Doug