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[209.132.180.67]) by mx.google.com with ESMTP id p76-v6si8208933itp.125.2018.05.07.13.41.45; Mon, 07 May 2018 13:41:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=bf7uFmD7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752841AbeEGUkZ (ORCPT + 99 others); Mon, 7 May 2018 16:40:25 -0400 Received: from mail.kernel.org ([198.145.29.99]:52280 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752081AbeEGUkX (ORCPT ); Mon, 7 May 2018 16:40:23 -0400 Received: from mail-qt0-f180.google.com (mail-qt0-f180.google.com [209.85.216.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 82EA72173F; Mon, 7 May 2018 20:40:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1525725622; bh=SsJe8HxRXLbI12hQLYOjUxK3rkhayRVy3gKYdwNfSSk=; h=In-Reply-To:References:From:Date:Subject:To:Cc:From; b=bf7uFmD7rwrp96UdiF0tH/rmxj846oLTdH++1PwOmACuMIgnODUwA7Z5OZaHtexBm 2dsIXHBttb209CB02fvGR8VlgneLL8+siOMwnjkiqvFbQ7nYy6+5r6MU9YE7pkBVSq vdBTUSbnUXsTtE7aIhO5jauut8VSI3Rn7vWYZ8xg= Received: by mail-qt0-f180.google.com with SMTP id h2-v6so38214099qtp.7; Mon, 07 May 2018 13:40:22 -0700 (PDT) X-Gm-Message-State: ALQs6tArcdP4Ne3JgMZyoVbIXiF8oVD7l6BKWi9SEVM5FNQlK12b4F9M MMqa3pUIzLYoSNDwx9zJWhj7DQSf3ZtaFA99BQ== X-Received: by 2002:a0c:f90b:: with SMTP id v11-v6mr19276280qvn.37.1525725621682; Mon, 07 May 2018 13:40:21 -0700 (PDT) MIME-Version: 1.0 Received: by 10.12.155.2 with HTTP; Mon, 7 May 2018 13:40:01 -0700 (PDT) In-Reply-To: References: <1525295174-15995-1-git-send-email-mgautam@codeaurora.org> <1525295174-15995-7-git-send-email-mgautam@codeaurora.org> <20180507155313.GA9696@rob-hp-laptop> From: Rob Herring Date: Mon, 7 May 2018 15:40:01 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v5 6/7] dt-bindings: phy-qcom-usb2: Add support to override tuning values To: Doug Anderson Cc: Manu Gautam , Kishon Vijay Abraham I , Stephen Boyd , devicetree@vger.kernel.org, LKML , Evan Green , Vivek Gautam , linux-arm-msm , Linux USB List Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, May 7, 2018 at 10:57 AM, Doug Anderson wrote: > Rob, > > On Mon, May 7, 2018 at 8:53 AM, Rob Herring wrote: >> On Thu, May 03, 2018 at 02:36:13AM +0530, Manu Gautam wrote: >>> To improve eye diagram for PHYs on different boards of same SOC, >>> some parameters may need to be changed. Provide device tree >>> properties to override these from board specific device tree >>> files. While at it, replace "qcom,qusb2-v2-phy" with compatible >>> string for USB2 PHY on sdm845 which was earlier added for >>> sdm845 only. >>> >>> Signed-off-by: Manu Gautam >>> --- >>> .../devicetree/bindings/phy/qcom-qusb2-phy.txt | 23 +++++++++++++- >>> include/dt-bindings/phy/phy-qcom-qusb2.h | 37 ++++++++++++++++++++++ >>> 2 files changed, 59 insertions(+), 1 deletion(-) >>> create mode 100644 include/dt-bindings/phy/phy-qcom-qusb2.h >>> >>> diff --git a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt >>> index 42c9742..03025d9 100644 >>> --- a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt >>> +++ b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt >>> @@ -6,7 +6,7 @@ QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets. >>> Required properties: >>> - compatible: compatible list, contains >>> "qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996, >>> - "qcom,qusb2-v2-phy" for QUSB2 V2 PHY. >>> + "qcom,sdm845-qusb2-phy" for 10nm PHY on sdm845. >>> >>> - reg: offset and length of the PHY register set. >>> - #phy-cells: must be 0. >>> @@ -27,6 +27,27 @@ Optional properties: >>> tuning parameter value for qusb2 phy. >>> >>> - qcom,tcsr-syscon: Phandle to TCSR syscon register region. >>> + - qcom,imp-res-offset-value: It is a 6 bit value that specifies offset to be >>> + added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY >>> + tuning parameter that may vary for different boards of same SOC. >>> + This property is applicable to only QUSB2 v2 PHY (sdm845). >>> + - qcom,hstx-trim-value: It is a 4 bit value that specifies tuning for HSTX >>> + output current. >>> + Possible range is - 15mA to 24mA (stepsize of 600 uA). >>> + See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. >>> + This property is applicable to only QUSB2 v2 PHY (sdm845). >>> + Default value is 22.2mA for sdm845. >>> + - qcom,preemphasis-level: It is a 2 bit value that specifies pre-emphasis level. >>> + Possible range is 0 to 15% (stepsize of 5%). >>> + See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. >>> + This property is applicable to only QUSB2 v2 PHY (sdm845). >>> + Default value is 10% for sdm845. >>> +- qcom,preemphasis-width: It is a 1 bit value that specifies how long the HSTX >>> + pre-emphasis (specified using qcom,preemphasis-level) must be in >>> + effect. Duration could be half-bit of full-bit. >> >> s/of/or/ >> >> But I'd just make this a boolean instead: qcom,preemphasis-half-bit > > I had this same comment in the post of v4. See > . Specifically, I said: > >> Perhaps just make this a boolean property. If it exists then you get >> the non-default case. AKA: if the default is full bit width, then >> you'd allow a boolean property "qcom,preemphasis-half-width" to >> override. If the default is half bit width then you'd allow >> "qcom,preemphasis-full-width" to override. > > Manu replied: > >> Default property value for an SOC is specified in driver and could vary from >> soc to soc. Hence, from board devicetree for different SOCs we might need >> to select separate widths overriding default driver values. >> Alternative is to have two bool properties each for half and full-width. Did >> you actually mean that? > > > IMHO given Manu's argument it seems fine to specify it the way he did. > Please advise if you agree or disagree. Okay. Reviewed-by: Rob Herring