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[209.132.180.67]) by mx.google.com with ESMTP id d9si23808403pfm.226.2018.05.07.17.38.40; Mon, 07 May 2018 17:38:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=WqtMQCgA; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753830AbeEHAiT (ORCPT + 99 others); Mon, 7 May 2018 20:38:19 -0400 Received: from mail-pg0-f67.google.com ([74.125.83.67]:44851 "EHLO mail-pg0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753735AbeEHAiQ (ORCPT ); Mon, 7 May 2018 20:38:16 -0400 Received: by mail-pg0-f67.google.com with SMTP id x145-v6so115953pgx.11 for ; Mon, 07 May 2018 17:38:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references:reply-to; bh=tFezesNvIX+WCGSDePcS+0ZnlHJF1XUMHe3fpAbs5h0=; b=WqtMQCgAiPr7YPXqD13h2xSD+Q7hjzCOHDKRohMHVrfS9SM1nyfM1aCPahhHWvlXmw vmt35r6mNZBxMB9jZt8l6hn92yyLQNyQ76gO8pMVjKuhPN81yuJZGtK9sSUz+/G5bc6G MmAYjEi42gPW475WdBEWg9+csdTuj7SjRmg8Z/pcN02G7Mqov7kQSaW+AJdFn4mbCYm3 2HHBWoHs9xD3paf/nRQwfgBUVrDXuGyWoDKIwzzGb8+y6TFRnmJxQn5/1Xyh0SR4fT9R s5PZ62jeZtbjgqRq0+Nubkoe2NEVnWeqt0noSEuttATzyY4MrojpkAPGdfk6DfPrUUo0 in6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:reply-to; bh=tFezesNvIX+WCGSDePcS+0ZnlHJF1XUMHe3fpAbs5h0=; b=SQG2xc/Be+tLxSEYs9PZiOs0kPZjs6F3L8osZFpcODTQ6iONZ6JdhlG/OPqYiEVc7x NspYWMJd+8r2jjYgT7tmzN3hjjFkJnKAQFf+0oiYnByZtOFy7MK0J4Adsv4c8d92A8av nIL8qTHbTmkWITjP2JerLkxJutdV2gaP0j6pV21M58I7HyH9KOtuXGoVNOvOqbJow2VG z9zEhr80MsKrg7r+0QdReHbLsfCb6fS/a9PMX2dwd1ZSKQaCcAU4QWlc6GULyGdaEH0m QuezoD2lZ+LHaXfRdN0C/bGx00JlFB94AmT9g0B76LEW4CI6+3otUz/sLp2oWzVUrFjW 8FNw== X-Gm-Message-State: ALKqPwcI2WP5QkUSRBmAZWZh5EjmLxbSQg9tZA93mhEyzfFMfAZZEjgE opUzuP3j4Y/FsMMK0KOo4dA= X-Received: by 10.167.131.84 with SMTP id z20mr513581pfm.166.1525739896332; Mon, 07 May 2018 17:38:16 -0700 (PDT) Received: from nvmetest.corp.microsoft.com ([2001:4898:80e8:6::4da]) by smtp.gmail.com with ESMTPSA id p126-v6sm37621458pga.28.2018.05.07.17.38.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 May 2018 17:38:15 -0700 (PDT) From: mhkelley58@gmail.com X-Google-Original-From: mikelley@microsoft.com To: gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, devel@linuxdriverproject.org, olaf@aepfle.de, apw@canonical.com, vkuznets@redhat.com, jasowang@redhat.com, leann.ogasawara@canonical.com, marcelo.cerri@canonical.com, sthemmin@microsoft.com, kys@microsoft.com Subject: [PATCH char-misc 1/2] Drivers: hv: vmbus: Remove x86 MSR refs in arch independent code Date: Mon, 7 May 2018 17:37:30 -0700 Message-Id: <1525739851-54919-2-git-send-email-mikelley@microsoft.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1525739851-54919-1-git-send-email-mikelley@microsoft.com> References: <1525739851-54919-1-git-send-email-mikelley@microsoft.com> Reply-To: mikelley@microsoft.com Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Michael Kelley In architecture independent code for manipulating Hyper-V synthetic timers and synthetic interrupts, pass in an ordinal number identifying the timer or interrupt, rather than an actual MSR register address. Then in x86/x64 specific code, map the ordinal number to the appropriate MSR. This change facilitates the introduction of an ARM64 version of Hyper-V, which uses the same synthetic timers and interrupts, but a different mechanism for accessing them. Signed-off-by: Michael Kelley --- arch/x86/include/asm/mshyperv.h | 12 ++++++++---- drivers/hv/hv.c | 20 ++++++++------------ 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/x86/include/asm/mshyperv.h b/arch/x86/include/asm/mshyperv.h index b90e796..caf9035 100644 --- a/arch/x86/include/asm/mshyperv.h +++ b/arch/x86/include/asm/mshyperv.h @@ -75,8 +75,10 @@ static inline void vmbus_signal_eom(struct hv_message *msg, u32 old_msg_type) } } -#define hv_init_timer(timer, tick) wrmsrl(timer, tick) -#define hv_init_timer_config(config, val) wrmsrl(config, val) +#define hv_init_timer(timer, tick) \ + wrmsrl(HV_X64_MSR_STIMER0_COUNT + (2*timer), tick) +#define hv_init_timer_config(timer, val) \ + wrmsrl(HV_X64_MSR_STIMER0_CONFIG + (2*timer), val) #define hv_get_simp(val) rdmsrl(HV_X64_MSR_SIMP, val) #define hv_set_simp(val) wrmsrl(HV_X64_MSR_SIMP, val) @@ -89,8 +91,10 @@ static inline void vmbus_signal_eom(struct hv_message *msg, u32 old_msg_type) #define hv_get_vp_index(index) rdmsrl(HV_X64_MSR_VP_INDEX, index) -#define hv_get_synint_state(int_num, val) rdmsrl(int_num, val) -#define hv_set_synint_state(int_num, val) wrmsrl(int_num, val) +#define hv_get_synint_state(int_num, val) \ + rdmsrl(HV_X64_MSR_SINT0 + int_num, val) +#define hv_set_synint_state(int_num, val) \ + wrmsrl(HV_X64_MSR_SINT0 + int_num, val) void hyperv_callback_vector(void); void hyperv_reenlightenment_vector(void); diff --git a/drivers/hv/hv.c b/drivers/hv/hv.c index 9b82549..96c403a 100644 --- a/drivers/hv/hv.c +++ b/drivers/hv/hv.c @@ -127,14 +127,14 @@ static int hv_ce_set_next_event(unsigned long delta, current_tick = hyperv_cs->read(NULL); current_tick += delta; - hv_init_timer(HV_X64_MSR_STIMER0_COUNT, current_tick); + hv_init_timer(0, current_tick); return 0; } static int hv_ce_shutdown(struct clock_event_device *evt) { - hv_init_timer(HV_X64_MSR_STIMER0_COUNT, 0); - hv_init_timer_config(HV_X64_MSR_STIMER0_CONFIG, 0); + hv_init_timer(0, 0); + hv_init_timer_config(0, 0); if (direct_mode_enabled) hv_disable_stimer0_percpu_irq(stimer0_irq); @@ -164,7 +164,7 @@ static int hv_ce_set_oneshot(struct clock_event_device *evt) timer_cfg.direct_mode = 0; timer_cfg.sintx = VMBUS_MESSAGE_SINT; } - hv_init_timer_config(HV_X64_MSR_STIMER0_CONFIG, timer_cfg.as_uint64); + hv_init_timer_config(0, timer_cfg.as_uint64); return 0; } @@ -298,8 +298,7 @@ int hv_synic_init(unsigned int cpu) hv_set_siefp(siefp.as_uint64); /* Setup the shared SINT. */ - hv_get_synint_state(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT, - shared_sint.as_uint64); + hv_get_synint_state(VMBUS_MESSAGE_SINT, shared_sint.as_uint64); shared_sint.vector = HYPERVISOR_CALLBACK_VECTOR; shared_sint.masked = false; @@ -308,8 +307,7 @@ int hv_synic_init(unsigned int cpu) else shared_sint.auto_eoi = true; - hv_set_synint_state(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT, - shared_sint.as_uint64); + hv_set_synint_state(VMBUS_MESSAGE_SINT, shared_sint.as_uint64); /* Enable the global synic bit */ hv_get_synic_state(sctrl.as_uint64); @@ -405,15 +403,13 @@ int hv_synic_cleanup(unsigned int cpu) put_cpu_ptr(hv_cpu); } - hv_get_synint_state(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT, - shared_sint.as_uint64); + hv_get_synint_state(VMBUS_MESSAGE_SINT, shared_sint.as_uint64); shared_sint.masked = 1; /* Need to correctly cleanup in the case of SMP!!! */ /* Disable the interrupt */ - hv_set_synint_state(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT, - shared_sint.as_uint64); + hv_set_synint_state(VMBUS_MESSAGE_SINT, shared_sint.as_uint64); hv_get_simp(simp.as_uint64); simp.simp_enabled = 0; -- 2.7.4