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[209.132.180.67]) by mx.google.com with ESMTP id h12-v6si4907543pls.278.2018.05.07.21.07.07; Mon, 07 May 2018 21:07:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=D0V7gNDO; dkim=pass header.i=@codeaurora.org header.s=default header.b=jxVpy8S1; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751237AbeEHEG5 (ORCPT + 99 others); Tue, 8 May 2018 00:06:57 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:52100 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750710AbeEHEGy (ORCPT ); Tue, 8 May 2018 00:06:54 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 3113A605A2; Tue, 8 May 2018 04:06:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1525752414; bh=U5M4qEtcWUAXlrMMe2PoZKPWKSPCnifxVGkCEj1GL5s=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=D0V7gNDOfQMInYYjq4K2LzOMzsYWL4kSdVOcvzHEUoaomEn3RP4wpqkSnq+hdBUDG tpDi0SkNRC8ilO5IlQ005JS9RjqlhjUIXgyqd+E24Lx+COLGU6XgSqPTRfQOf2Au67 2PjMN1NUM59X0ZsGEW+xIBJzgvgp9ZIjTGIgHdxg= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from [10.206.24.26] (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: mgautam@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id B963E6022C; Tue, 8 May 2018 04:06:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1525752413; bh=U5M4qEtcWUAXlrMMe2PoZKPWKSPCnifxVGkCEj1GL5s=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=jxVpy8S1pYu1bmBrLGvoWFaBZHvX7wlIF41tmCz0Ia5ZmvyWR0k+4g7EbbQ1kPv3Y /ggWEF278FUSe9i8lxfPdo5Pn0sqmrXL3GA5dUh7HoIcSlDxNhGT7hYTKcEySZ55U8 AF1Vi6r33k+gBHNeF4Cj6kd4EkTrtP3E78NUS/oM= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B963E6022C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=mgautam@codeaurora.org Subject: Re: [PATCH v3 2/3] usb: dwc3: Add Qualcomm DWC3 glue driver To: balbi@kernel.org, robh@kernel.org, andy.gross@linaro.org Cc: linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, linux-arm-msm@vger.kernel.org, Greg Kroah-Hartman References: <1525459689-1358-1-git-send-email-mgautam@codeaurora.org> <1525459689-1358-3-git-send-email-mgautam@codeaurora.org> From: Manu Gautam Message-ID: <7bc35d33-c819-fb64-353c-f64dce08505f@codeaurora.org> Date: Tue, 8 May 2018 09:36:48 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <1525459689-1358-3-git-send-email-mgautam@codeaurora.org> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/5/2018 12:18 AM, Manu Gautam wrote: > DWC3 controller on Qualcomm SOCs has a Qscratch wrapper. > Some of its uses are described below resulting in need to > have a separate glue driver instead of using dwc3-of-simple: > - It exposes register interface to override vbus-override > and lane0-pwr-present signals going to hardware. These > must be updated in peripheral mode for DWC3 if vbus lines > are not connected to hardware block. Otherwise RX termination > in SS mode or DP pull-up is not applied by device controller. > - pwr_events_irq_stat support to check if USB2 PHY is in L2 state > before glue driver proceeds with suspend. > - Support for wakeup interrupts lines that are asserted whenever > there is any wakeup event on USB3 or USB2 bus. > - Support to replace pip3 clock going to DWC3 with utmi clock > for hardware configuration where SSPHY is not used with DWC3. > > Signed-off-by: Manu Gautam [snip] > +static const struct of_device_id dwc3_qcom_of_match[] = { > + { .compatible = "qcom,dwc3" }, I should also add SOC specific compatibles. Will do that in next patch. -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project