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[209.132.180.67]) by mx.google.com with ESMTP id t135-v6si19764601pgc.656.2018.05.08.06.27.45; Tue, 08 May 2018 06:27:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=LZyin90f; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755208AbeEHN1L (ORCPT + 99 others); Tue, 8 May 2018 09:27:11 -0400 Received: from mail-yw0-f195.google.com ([209.85.161.195]:37066 "EHLO mail-yw0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755193AbeEHN1J (ORCPT ); Tue, 8 May 2018 09:27:09 -0400 Received: by mail-yw0-f195.google.com with SMTP id u83-v6so9641872ywc.4; Tue, 08 May 2018 06:27:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7Yqxn8f02xGv64GoRNMIvu3lBrnW81qZRBJYu4SXOtE=; b=LZyin90fGFHSqZfBATuqbKpo664Yec9UdKnZrt4r/osJJR/Q2mvfVBtIlgYg5tGGFb 7YiuZYLic4p7hG5EqkH3AmIQjGGVgwwoz0BCoLAxg7fRzGUWipiWDALy5jx0bj8sHXNo KnTKzDa2982UPwkii2/+6qZ/18QkKsUdkypqdlc9dyBxmxE2LLaTmAH5kIlSjjyw1F8/ BlRUJSZnLZQaiFTKEKOvCDciHeu3fClWbZ2A4dv1OkBAOmv6IiXXwNQV+J0aV13kWGcK oeP66WU5wIHSfEJObN3DN2UktfosfrvJY7UkuR5g3DhWVkSpRabjLK0z/25q9InJM0vU liYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7Yqxn8f02xGv64GoRNMIvu3lBrnW81qZRBJYu4SXOtE=; b=I7yrnQu1ErFhZZo2YNiBMgENptYTxa+g2bBIKKwA8EqKMMU7tu2JPNn38tMTviu+AT D2RHprNutrLRCHQuM1Z8827lOr1SIkeoQYV8gsX31GKRaE4faDuiR2no2caJINjJ+AwD nbPrIBWZppZLlglLpmunS2M65fthOx0pJMFVPY16SzaOgJqovoO73RRu3Qb5ziKq6Leb HC/pkVHkqymYegqHl/Bpn9WopKHxw/BX8nuvw72d6XLVD/AgYGxTA7CWmr+/gZXzKgTO TaJ48q/++oBEtySz+hqpIJsi7lkYKbl07GlwaDTAJN/FESVFBwiIg1H8tPGaBb8r6IZp uAkQ== X-Gm-Message-State: ALQs6tBaevrkm2ySdnlCmDXM8Gm7fVq1e7f1HwWoZ+K7r3VgLqsb9nMd ov9B6yWWptBeKuJ6TBODzHi2nQ== X-Received: by 2002:a0d:f0c1:: with SMTP id z184-v6mr22193172ywe.143.1525786028389; Tue, 08 May 2018 06:27:08 -0700 (PDT) Received: from localhost ([72.188.97.40]) by smtp.gmail.com with ESMTPSA id k8-v6sm5574782ywa.32.2018.05.08.06.27.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 May 2018 06:27:08 -0700 (PDT) From: William Breathitt Gray To: linus.walleij@linaro.org Cc: linux-gpio@vger.kernel.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, William Breathitt Gray Subject: [PATCH v2 2/7] gpio: 104-dio-48e: Utilize for_each_set_port_word macro Date: Tue, 8 May 2018 09:27:02 -0400 Message-Id: X-Mailer: git-send-email 2.17.0 In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Replace boilerplate code in get_multiple/set_multiple callbacks with for_each_set_port_word macro to simplify code and improve clarity. Signed-off-by: William Breathitt Gray --- drivers/gpio/gpio-104-dio-48e.c | 67 ++++++++------------------------- 1 file changed, 16 insertions(+), 51 deletions(-) diff --git a/drivers/gpio/gpio-104-dio-48e.c b/drivers/gpio/gpio-104-dio-48e.c index 9c4e07fcb74b..843f1c71e814 100644 --- a/drivers/gpio/gpio-104-dio-48e.c +++ b/drivers/gpio/gpio-104-dio-48e.c @@ -183,46 +183,23 @@ static int dio48e_gpio_get(struct gpio_chip *chip, unsigned offset) return !!(port_state & mask); } +static const size_t ports[] = { 0, 1, 2, 4, 5, 6 }; + static int dio48e_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, unsigned long *bits) { struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); size_t i; - static const size_t ports[] = { 0, 1, 2, 4, 5, 6 }; - const unsigned int gpio_reg_size = 8; - unsigned int bits_offset; - size_t word_index; - unsigned int word_offset; - unsigned long word_mask; - const unsigned long port_mask = GENMASK(gpio_reg_size - 1, 0); + size_t word; + unsigned int offset; unsigned long port_state; /* clear bits array to a clean slate */ bitmap_zero(bits, chip->ngpio); - /* get bits are evaluated a gpio port register at a time */ - for (i = 0; i < ARRAY_SIZE(ports); i++) { - /* gpio offset in bits array */ - bits_offset = i * gpio_reg_size; - - /* word index for bits array */ - word_index = BIT_WORD(bits_offset); - - /* gpio offset within current word of bits array */ - word_offset = bits_offset % BITS_PER_LONG; - - /* mask of get bits for current gpio within current word */ - word_mask = mask[word_index] & (port_mask << word_offset); - if (!word_mask) { - /* no get bits in this port so skip to next one */ - continue; - } - - /* read bits from current gpio port */ + for_each_set_port_word(i, word, offset, mask, ARRAY_SIZE(ports), 8) { port_state = inb(dio48egpio->base + ports[i]); - - /* store acquired bits at respective bits array offset */ - bits[word_index] |= port_state << word_offset; + bits[word] |= port_state << offset; } return 0; @@ -252,37 +229,25 @@ static void dio48e_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask, unsigned long *bits) { struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); - unsigned int i; - const unsigned int gpio_reg_size = 8; - unsigned int port; - unsigned int out_port; + size_t i; + size_t word; + unsigned int offset; + unsigned int iomask; unsigned int bitmask; unsigned long flags; - /* set bits are evaluated a gpio register size at a time */ - for (i = 0; i < chip->ngpio; i += gpio_reg_size) { - /* no more set bits in this mask word; skip to the next word */ - if (!mask[BIT_WORD(i)]) { - i = (BIT_WORD(i) + 1) * BITS_PER_LONG - gpio_reg_size; - continue; - } - - port = i / gpio_reg_size; - out_port = (port > 2) ? port + 1 : port; - bitmask = mask[BIT_WORD(i)] & bits[BIT_WORD(i)]; + for_each_set_port_word(i, word, offset, mask, ARRAY_SIZE(ports), 8) { + iomask = mask[word] >> offset; + bitmask = iomask & (bits[word] >> offset); raw_spin_lock_irqsave(&dio48egpio->lock, flags); /* update output state data and set device gpio register */ - dio48egpio->out_state[port] &= ~mask[BIT_WORD(i)]; - dio48egpio->out_state[port] |= bitmask; - outb(dio48egpio->out_state[port], dio48egpio->base + out_port); + dio48egpio->out_state[i] &= ~iomask; + dio48egpio->out_state[i] |= bitmask; + outb(dio48egpio->out_state[i], dio48egpio->base + ports[i]); raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); - - /* prepare for next gpio register set */ - mask[BIT_WORD(i)] >>= gpio_reg_size; - bits[BIT_WORD(i)] >>= gpio_reg_size; } } -- 2.17.0