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[209.132.180.67]) by mx.google.com with ESMTP id j10si14550576pfn.87.2018.05.08.10.25.15; Tue, 08 May 2018 10:25:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=PrROCKJ3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932706AbeEHRX3 (ORCPT + 99 others); Tue, 8 May 2018 13:23:29 -0400 Received: from mail-io0-f195.google.com ([209.85.223.195]:34101 "EHLO mail-io0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932538AbeEHRVC (ORCPT ); Tue, 8 May 2018 13:21:02 -0400 Received: by mail-io0-f195.google.com with SMTP id p124-v6so39364430iod.1 for ; Tue, 08 May 2018 10:21:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wktoaVW3M97S2UFmocbw1UefadbGqTycJM5C8xIUnBw=; b=PrROCKJ3QbgyQRskehQdsMZsriHJyTp3nsN+siDmMaKOBpyohBSv4XS13lBqb823/h HgncPNt47YqmSxxRzOwMn6nkvqcAre3Yh+QgOR/GL6EKix880KJPsAbeJeexMd+M9H79 p+eN8opz+TXI4IeBhmJg74KqT52DOsae5/KIbYCZMb9lxSWnzUE6yZgUkF7zjsPw/wZg MBvPog/tveHLhLZoimLIrx10sARVpUmXM8UR2a5waayLCKWKj1uD8gl6cqmaWgvC47e+ nM3f7GKd8uOq19CoMd6gvzwmhcnK8xjEVBf5dSIPOOULN4JVf3tbpeGIId2pKhdVW5Ck D/hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wktoaVW3M97S2UFmocbw1UefadbGqTycJM5C8xIUnBw=; b=MX509ozYneb8mMLWr/XdLCNezTaaJP4YedOc/91zzYTEQ1kutVEiiPXdxfFzlPFV5a nmR21B/Kynk/oCQExD7NGR+87Cr6rfQKJ8lTHgxTlitmG01SwSicFLtlJkpKIw+sufFI bbZbrscahXC+mvz3AUkdrXdsZBMCbfLPM7jZcVa3naLGs77iNJ78pmTXkFIghK700u7+ P4cFvnbwQ3BWSRnkarweJYpUNGAlWRD9OPGtEOGaJn7T63Js83RFvT/hPaOoXdk9FUs2 n60CCBXIw1tRxQcUB8Vg6r7nKa9nhGZyFWlxY/XIVu9XmdUnHBZBTjEzsyM4BFURv1gU q6wQ== X-Gm-Message-State: ALQs6tA2IkmhNpC8S1Uc/EAJpH+K3FhC5XSuYfEqBwKBS2xhhKOlIuL0 yvH2T0sEAo3VzyiM711Vde8= X-Received: by 2002:a6b:11df:: with SMTP id 92-v6mr45070363ior.156.1525800061845; Tue, 08 May 2018 10:21:01 -0700 (PDT) Received: from localhost.localdomain ([2605:a000:1316:4462:80cc:335d:e307:b5cb]) by smtp.googlemail.com with ESMTPSA id k62-v6sm13160209ioo.23.2018.05.08.10.21.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 08 May 2018 10:21:01 -0700 (PDT) From: Connor McAdams Cc: o-takashi@sakamocchi.jp, Connor McAdams , Jaroslav Kysela , Takashi Iwai , =?UTF-8?q?J=C3=A9r=C3=A9my=20Lefaure?= , alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 08/13] ALSA: hda/ca0132: Add dsp setup + gpio functions for r3di Date: Tue, 8 May 2018 13:20:08 -0400 Message-Id: <1525800015-2920-9-git-send-email-conmanx360@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1525800015-2920-1-git-send-email-conmanx360@gmail.com> References: <1525800015-2920-1-git-send-email-conmanx360@gmail.com> To: unlisted-recipients:; (no To-header on input) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Adds dsp setup functions for Recon3Di as well as the GPIO functions specific to it. Signed-off-by: Connor McAdams --- sound/pci/hda/patch_ca0132.c | 149 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 148 insertions(+), 1 deletion(-) diff --git a/sound/pci/hda/patch_ca0132.c b/sound/pci/hda/patch_ca0132.c index 37609bd..7a9d505 100644 --- a/sound/pci/hda/patch_ca0132.c +++ b/sound/pci/hda/patch_ca0132.c @@ -2904,6 +2904,76 @@ static void ca0132_gpio_setup(struct hda_codec *codec) } /* + * GPIO control functions for the Recon3D integrated. + */ + +enum r3di_gpio_bit { + /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */ + R3DI_MIC_SELECT_BIT = 1, + /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */ + R3DI_OUT_SELECT_BIT = 2, + /* + * I dunno what this actually does, but it stays on until the dsp + * is downloaded. + */ + R3DI_GPIO_DSP_DOWNLOADING = 3, + /* + * Same as above, no clue what it does, but it comes on after the dsp + * is downloaded. + */ + R3DI_GPIO_DSP_DOWNLOADED = 4 +}; + +enum r3di_mic_select { + /* Set GPIO bit 1 to 0 for rear mic */ + R3DI_REAR_MIC = 0, + /* Set GPIO bit 1 to 1 for front microphone*/ + R3DI_FRONT_MIC = 1 +}; + +enum r3di_out_select { + /* Set GPIO bit 2 to 0 for headphone */ + R3DI_HEADPHONE_OUT = 0, + /* Set GPIO bit 2 to 1 for speaker */ + R3DI_LINE_OUT = 1 +}; +enum r3di_dsp_status { + /* Set GPIO bit 3 to 1 until DSP is downloaded */ + R3DI_DSP_DOWNLOADING = 0, + /* Set GPIO bit 4 to 1 once DSP is downloaded */ + R3DI_DSP_DOWNLOADED = 1 +}; + +static void r3di_gpio_dsp_status_set(struct hda_codec *codec, + enum r3di_dsp_status dsp_status) +{ + unsigned int cur_gpio; + + /* Get the current GPIO Data setup */ + cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); + + switch (dsp_status) { + case R3DI_DSP_DOWNLOADING: + cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING); + snd_hda_codec_write(codec, codec->core.afg, 0, + AC_VERB_SET_GPIO_DATA, cur_gpio); + break; + case R3DI_DSP_DOWNLOADED: + /* Set DOWNLOADING bit to 0. */ + cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING); + + snd_hda_codec_write(codec, codec->core.afg, 0, + AC_VERB_SET_GPIO_DATA, cur_gpio); + + cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED); + break; + } + + snd_hda_codec_write(codec, codec->core.afg, 0, + AC_VERB_SET_GPIO_DATA, cur_gpio); +} + +/* * PCM callbacks */ static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo, @@ -4539,6 +4609,30 @@ static void ca0132_refresh_widget_caps(struct hda_codec *codec) } /* + * Recon3Di r3di_setup_defaults sub functions. + */ + +static void r3di_dsp_initial_mic_setup(struct hda_codec *codec) +{ + unsigned int tmp; + + /* Mic 1 Setup */ + chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); + chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); + /* This ConnPointID is unique to Recon3Di. Haven't seen it elsewhere */ + chipio_set_conn_rate(codec, 0x0F, SR_96_000); + tmp = FLOAT_ONE; + dspio_set_uint_param(codec, 0x80, 0x00, tmp); + + /* Mic 2 Setup, even though it isn't connected on SBZ */ + chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000); + chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000); + chipio_set_conn_rate(codec, 0x0F, SR_96_000); + tmp = FLOAT_ZERO; + dspio_set_uint_param(codec, 0x80, 0x01, tmp); +} + +/* * Initialize Sound Blaster Z analog microphones. */ static void sbz_init_analog_mics(struct hda_codec *codec) @@ -4700,6 +4794,50 @@ static void ca0132_setup_defaults(struct hda_codec *codec) } /* + * Setup default parameters for Recon3Di DSP. + */ + +static void r3di_setup_defaults(struct hda_codec *codec) +{ + struct ca0132_spec *spec = codec->spec; + unsigned int tmp; + int num_fx; + int idx, i; + + if (spec->dsp_state != DSP_DOWNLOADED) + return; + + + r3di_dsp_initial_mic_setup(codec); + + /*remove DSP headroom*/ + tmp = FLOAT_ZERO; + dspio_set_uint_param(codec, 0x96, 0x3C, tmp); + + /* set WUH source */ + tmp = FLOAT_TWO; + dspio_set_uint_param(codec, 0x31, 0x00, tmp); + chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); + + /* Set speaker source? */ + dspio_set_uint_param(codec, 0x32, 0x00, tmp); + + r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED); + + /* Setup effect defaults */ + num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; + for (idx = 0; idx < num_fx; idx++) { + for (i = 0; i <= ca0132_effects[idx].params; i++) { + dspio_set_uint_param(codec, + ca0132_effects[idx].mid, + ca0132_effects[idx].reqs[i], + ca0132_effects[idx].def_vals[i]); + } + } + +} + +/* * Setup default parameters for the Sound Blaster Z DSP. A lot more going on * than the Chromebook setup. */ @@ -5397,6 +5535,7 @@ static void ca0132_alt_init(struct hda_codec *codec) codec_dbg(codec, "R3DI alt_init"); ca0132_gpio_init(codec); ca0132_gpio_setup(codec); + r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING); r3di_pre_dsp_setup(codec); snd_hda_sequence_write(codec, spec->chip_init_verbs); snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4); @@ -5445,21 +5584,29 @@ static int ca0132_init(struct hda_codec *codec) ca0132_init_unsol(codec); ca0132_init_params(codec); ca0132_init_flags(codec); + snd_hda_sequence_write(codec, spec->base_init_verbs); if (spec->quirk != QUIRK_NONE) ca0132_alt_init(codec); ca0132_download_dsp(codec); + ca0132_refresh_widget_caps(codec); if (spec->quirk == QUIRK_SBZ) writew(0x0107, spec->mem_base + 0x320); - if (spec->quirk != QUIRK_SBZ) { + switch (spec->quirk) { + case QUIRK_R3DI: + r3di_setup_defaults(codec); + break; + case QUIRK_NONE: + case QUIRK_ALIENWARE: ca0132_setup_defaults(codec); ca0132_init_analog_mic2(codec); ca0132_init_dmic(codec); + break; } for (i = 0; i < spec->num_outputs; i++) -- 2.7.4