Received: by 10.192.165.148 with SMTP id m20csp4989277imm; Tue, 8 May 2018 19:22:15 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpkSPY10BG4uuejafCC9npmD8CtVJ7gv/wWpaAzctkXlXoxaRfDJ7nnTooN+ZxZXrFXe81m X-Received: by 2002:a17:902:680c:: with SMTP id h12-v6mr44549637plk.113.1525832534949; Tue, 08 May 2018 19:22:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525832534; cv=none; d=google.com; s=arc-20160816; b=ZbixXMlxPnimNyvHeK57GA0n+bfH+4TCt1Ap9YwPeziSprWn3O4qFqV/fDV8b9fQ4D KfLPwbiy2F6KJMtqFSCyYLfY6rKJErESieDMu5RqcB7+5ChNT7sGWt3CMCVFfdvPdIlY nLVnyMUhgswCsy0rT7uVLw9QtyGwN0hD+UDfQ/Z9k0WTfyZSjhG+7P7vxPZCccOiN2qs AT1NSoUrGFukyhFCDncUQeKGc7DBXnSja/8+Mo4rl8vDe2RFHWE6e5zma44QjmH5f7My CkFQxPU7XUnE5OSHGo6Zq92toNEqmadrSgXKnlCOE0KHReOf0IusRDfhjfYRq80kUkDo OMeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:in-reply-to :references:subject:cc:to:mime-version:user-agent:from:date :message-id:arc-authentication-results; bh=7Vdftzdznw8+TM4aKR/gH8xTsoM6i9byJXl2vZU3zFw=; b=iJGpSZsnXbL7Sakmh6pqeoByzrj3ACNWRa7TfbLlibRLw2hBzag5kmNiEowMbE6i66 piZdc4XZ2rZYRrO9ed5hG505Q8agjbbiPAGuzn61gnLEMNODM4+h7gOQgOOdSQEpNLJG uFt/4MiZM3SQaBr6P4zOb6xVqYMeqTtYlVJ9t74uVsAhm1B/30rewi0yhc97Yj3zUMs2 hvnl0Jrh7eK+dQGt0YxoJoeACAaAHlZfAmI5ABX93um3kbnbr5MrEbdHL0eGa7HjtZ4M sqoLov0LmK0yo/zSb1IKxBhqGMcYxtf6EVf/a5DbSinhCyAgek7OBecXMo/4VrwXLhIM vtbw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 43-v6si11483079plb.511.2018.05.08.19.21.59; Tue, 08 May 2018 19:22:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933522AbeEICVs (ORCPT + 99 others); Tue, 8 May 2018 22:21:48 -0400 Received: from regular1.263xmail.com ([211.150.99.132]:35649 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932579AbeEICVq (ORCPT ); Tue, 8 May 2018 22:21:46 -0400 Received: from jeffy.chen?rock-chips.com (unknown [192.168.167.208]) by regular1.263xmail.com (Postfix) with ESMTP id ACB3593FD; Wed, 9 May 2018 10:21:40 +0800 (CST) X-263anti-spam: KSV:0;BIG:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ADDR-CHECKED4: 1 X-ABS-CHECKED: 1 X-SKE-CHECKED: 1 X-ANTISPAM-LEVEL: 2 Received: from [172.16.22.179] (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id EF0F03D2; Wed, 9 May 2018 10:21:35 +0800 (CST) X-IP-DOMAINF: 1 X-RL-SENDER: jeffy.chen@rock-chips.com X-FST-TO: dianders@chromium.org X-SENDER-IP: 103.29.142.67 X-LOGIN-NAME: jeffy.chen@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: cjf@rock-chips.com X-DNS-TYPE: 0 Received: from [172.16.22.179] (unknown [103.29.142.67]) by smtp.263.net (Postfix) whith ESMTP id 2027PY7JL1; Wed, 09 May 2018 10:21:40 +0800 (CST) Message-ID: <5AF25B2E.8080901@rock-chips.com> Date: Wed, 09 May 2018 10:21:34 +0800 From: JeffyChen User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:19.0) Gecko/20130126 Thunderbird/19.0 MIME-Version: 1.0 To: Doug Anderson , Brian Norris CC: LKML , =?UTF-8?B?SGVpa28gU3TDvGJuZXI=?= , "open list:ARM/Rockchip SoC..." , Linus Walleij , linux-gpio@vger.kernel.org, Linux ARM Subject: Re: [RESEND PATCH] pinctrl: rockchip: Disable interrupt when changing it's capability References: <20180503065553.7762-1-jeffy.chen@rock-chips.com> <20180507221511.GA6448@rodete-desktop-imager.corp.google.com> <5AF0FF18.1050905@rock-chips.com> <20180508015623.GA61455@rodete-desktop-imager.corp.google.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Doug, On 05/09/2018 03:46 AM, Doug Anderson wrote: > One note is that in the case Brian points at (where we need to > simulate EDGE_BOTH by swapping edges) we purposely ignored the TRM and > we needed to do that to avoid losing interrupts. For details, see > commit 53b1bfc76df2 ("pinctrl: rockchip: Avoid losing interrupts when > supporting both edges"). We did this because: > > 1. We believed that the IP block in Rockchip SoCs has nearly the same > logic as "gpio-dwapb.c" and that's what "gpio-dwapb.c" did. > hmm, but i saw the gpio-dwapb.c actually toggle trigger after handle irq, which might avoid the race Brian mentioned: + generic_handle_irq(gpio_irq); + irq_status &= ~BIT(hwirq); + + if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK) + == IRQ_TYPE_EDGE_BOTH) + dwapb_toggle_trigger(gpio, hwirq); and i also saw ./qcom/pinctrl-msm.c do the toggle(msm_gpio_update_dual_edge_pos) at the end of msm_gpio_irq_set_type and msm_gpio_irq_ack, that seems can avoid the polarity races too. > 2. We were actually losing real interrupts and this was the only way > we could figure out how to fix it. > > When I tested that back in the day I was fairly convinced that we > weren't losing any interrupts in the EDGE_BOTH case after my fix, but > I certainly could have messed up. > > > For the EDGE_BOTH case it was important not to lose an interrupt > because, as you guys are talking about, we could end up configured the > wrong way. I think in your case where you're just picking one > polarity losing an interrupt shouldn't matter since it's undefined > exactly if an edge happens while you're in the middle of executing > rockchip_irq_set_type(). Is that right? right, so we now have 2 cases: rockchip_irq_demux/ rockchip_irq_set_type if i'm right about the spurious irq(only happen when set rising for a high gpio, or set falling for a low gpio), then: 1/ rockchip_irq_demux it's important to not losing irqs in this case, maybe we can a) ack irq b) update polarity for edge both irq we don't need to disable irq in b), since we would not hit the spurious irq cases here(always check gpio level to toggle it) 2/ rockchip_irq_set_type it's important to not having spurious irqs so we can disable irq during changing polarity only in these case: ((rising && gpio is heigh) || (falling && gpio is low)) i'm still confirming the spurious irq with IC guys. > > > -Doug > > >