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[209.132.180.67]) by mx.google.com with ESMTP id t127-v6si45508pgc.519.2018.05.08.21.02.12; Tue, 08 May 2018 21:02:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=yQfgzXWu; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750816AbeEIEBD (ORCPT + 99 others); Wed, 9 May 2018 00:01:03 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:51293 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750722AbeEIEBB (ORCPT ); Wed, 9 May 2018 00:01:01 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w4940xVT003820; Tue, 8 May 2018 23:00:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1525838459; bh=GmourOEw8jZoCqWxSniRD8lLeamWtwlywP1d6rloyuk=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=yQfgzXWuuw8gAICjCMYN2spQL0qBcUWU+DhL4Y8ykZDbZ4L62ZpkI7br+iI0Crwbs ojMEShZaQWMPGMwkRvBO7degpoivntWwrKeet4LRY8jOiog4ktv47ycECkavKh3l7f vX+A94OvemTMe7gnHSaQptUV0KxWTmsdqB5538NU= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w4940xf5002219; Tue, 8 May 2018 23:00:59 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Tue, 8 May 2018 23:00:59 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Tue, 8 May 2018 23:00:59 -0500 Received: from [172.24.191.45] (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w4940umE022421; Tue, 8 May 2018 23:00:57 -0500 Subject: Re: [PATCH 0/4] ARM: dts: am437x boards: Correct (again) tps65218 irq type To: Tony Lindgren , Peter Ujfalusi CC: , , , References: <20180508132053.5471-1-peter.ujfalusi@ti.com> <20180508141600.GT98604@atomide.com> From: Keerthy Message-ID: <4b4100d0-85e1-659b-8f7e-b3d4b3925e82@ti.com> Date: Wed, 9 May 2018 09:30:56 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: <20180508141600.GT98604@atomide.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tuesday 08 May 2018 07:46 PM, Tony Lindgren wrote: > * Peter Ujfalusi [180508 13:22]: >> Hi, >> >> While based on the datasheet of tps65218 the INT is low active, the GIC_SPI >> does not support anythin but IRQ_TYPE_LEVEL_HIGH or IRQ_TYPE_EDGE_RISING: >> >> [ 2.761814] genirq: Setting trigger mode 8 for irq 102 failed (irq_chip_set_type_parent+0x0/0x30) >> [ 2.770913] tps65218 0-0024: Failed to request IRQ 102 for tps65218: -22 >> [ 2.777854] tps65218: probe of 0-0024 failed with error -22 > > So does the tps65218 have some register to control the interrupt > direction or is it's datasheet wrong? > > BTW, ADC might be a good test case for PMIC interrupt if it has one. There is no ADC on this PMIC. > >> Use LEVEL_HIGH for the interrupt as it looks to be the correct setting: >> INTn of tps65218 is connected to NMIn of the SoC. >> >> The offending patches are only in linux-next. > > OK > > Regards, > > Tony >