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[209.132.180.67]) by mx.google.com with ESMTP id z3-v6si22226121pgr.171.2018.05.09.10.31.56; Wed, 09 May 2018 10:32:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@lechnology.com header.s=default header.b=Yid/8N6g; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965853AbeEIR1Y (ORCPT + 99 others); Wed, 9 May 2018 13:27:24 -0400 Received: from vern.gendns.com ([206.190.152.46]:51902 "EHLO vern.gendns.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935538AbeEIR1C (ORCPT ); Wed, 9 May 2018 13:27:02 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lechnology.com; s=default; h=References:In-Reply-To:Message-Id:Date:Subject :Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=bGy99CtpszhmjkZhvuf5k4jGqr+8VrImX0i6DPSSmj8=; b=Yid/8N6gdWkn6I6kDfmm9tii5 peB2QIiR49KIoaizeAxlR3hlhE7bvfx3t/2IJdw8067cyeKCyIMBLt6Jg1G3ZUnhop7tw9Zvli24a 0CeDX4loAamnG8rMyWyukkxh9Ur4WG8q8WowdopVsE/emqJ1uaaMS50B2jPdFuCmQJWvZQf5qMNYK IyD+wC7RO42xPmb3GIL+XNtl3uaBcQZx57sa5eNwUKifIn69keNWpNpyp9axQcDKmjIXd3sIv9Ap8 I/2eMvjHTaypJc6wBvGCFkmbc97/0pxwGOLq6hjilp7x6YbINo+c0UTWCksMjMTEcDNyfCyaRfnBc mTTl3fEPA==; Received: from 108-198-5-147.lightspeed.okcbok.sbcglobal.net ([108.198.5.147]:58616 helo=freyr.lechnology.com) by vern.gendns.com with esmtpsa (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.89_1) (envelope-from ) id 1fGSrR-00EzgW-2s; Wed, 09 May 2018 13:26:41 -0400 From: David Lechner To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Sekhar Nori , Kevin Hilman , Bartosz Golaszewski , Adam Ford , linux-kernel@vger.kernel.org, David Lechner Subject: [PATCH v10 02/27] clk: davinci: da850-pll: change PLL0 to CLK_OF_DECLARE Date: Wed, 9 May 2018 12:25:41 -0500 Message-Id: <20180509172606.29387-3-david@lechnology.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180509172606.29387-1-david@lechnology.com> References: <20180509172606.29387-1-david@lechnology.com> X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - vern.gendns.com X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - lechnology.com X-Get-Message-Sender-Via: vern.gendns.com: authenticated_id: davidmain+lechnology.com/only user confirmed/virtual account not confirmed X-Authenticated-Sender: vern.gendns.com: davidmain@lechnology.com X-Source: X-Source-Args: X-Source-Dir: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org PLL0 on davinci/da850-type device needs to be registered early in boot because it is needed for clocksource/clockevent. Change the driver to use CLK_OF_DECLARE for this special case. Signed-off-by: David Lechner --- v10 changes: - removed duplicate warning message v9 changes: - new patch in v9 drivers/clk/davinci/pll-da850.c | 21 +++++++++++++++++---- drivers/clk/davinci/pll.c | 4 +++- drivers/clk/davinci/pll.h | 2 +- 3 files changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/clk/davinci/pll-da850.c b/drivers/clk/davinci/pll-da850.c index 00a6ece7b524..fde4642a993f 100644 --- a/drivers/clk/davinci/pll-da850.c +++ b/drivers/clk/davinci/pll-da850.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include #include #include @@ -135,11 +137,22 @@ static const struct davinci_pll_sysclk_info *da850_pll0_sysclk_info[] = { NULL }; -int of_da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) +void of_da850_pll0_init(struct device_node *node) { - return of_davinci_pll_init(dev, dev->of_node, &da850_pll0_info, - &da850_pll0_obsclk_info, - da850_pll0_sysclk_info, 7, base, cfgchip); + void __iomem *base; + struct regmap *cfgchip; + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s: ioremap failed\n", __func__); + return; + } + + cfgchip = syscon_regmap_lookup_by_compatible("ti,da830-cfgchip"); + + of_davinci_pll_init(NULL, node, &da850_pll0_info, + &da850_pll0_obsclk_info, + da850_pll0_sysclk_info, 7, base, cfgchip); } static const struct davinci_pll_clk_info da850_pll1_info = { diff --git a/drivers/clk/davinci/pll.c b/drivers/clk/davinci/pll.c index f362f10d8459..dcfa780f828a 100644 --- a/drivers/clk/davinci/pll.c +++ b/drivers/clk/davinci/pll.c @@ -770,8 +770,10 @@ static struct davinci_pll_platform_data *davinci_pll_get_pdata(struct device *de return pdata; } +/* needed in early boot for clocksource/clockevent */ +CLK_OF_DECLARE(da850_pll0, "ti,da850-pll0", of_da850_pll0_init); + static const struct of_device_id davinci_pll_of_match[] = { - { .compatible = "ti,da850-pll0", .data = of_da850_pll0_init }, { .compatible = "ti,da850-pll1", .data = of_da850_pll1_init }, { } }; diff --git a/drivers/clk/davinci/pll.h b/drivers/clk/davinci/pll.h index 562652fc0759..b2e5c4496645 100644 --- a/drivers/clk/davinci/pll.h +++ b/drivers/clk/davinci/pll.h @@ -123,7 +123,7 @@ int of_davinci_pll_init(struct device *dev, struct device_node *node, /* Platform-specific callbacks */ int da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); -int of_da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); +void of_da850_pll0_init(struct device_node *node); int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); int dm355_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); -- 2.17.0