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Date:   Wed, 9 May 2018 21:05:36 +0200
From:   Andrew Lunn <andrew@lunn.ch>
To:     Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Cc:     netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
        kernel@savoirfairelinux.com, davem@davemloft.net,
        f.fainelli@gmail.com
Subject: Re: [PATCH net-next 1/3] net: dsa: mv88e6xxx: add a cascade port op
Message-ID: <20180509190536.GD21718@lunn.ch>
References: <20180509153851.10207-1-vivien.didelot@savoirfairelinux.com>
 <20180509153851.10207-2-vivien.didelot@savoirfairelinux.com>
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On Wed, May 09, 2018 at 11:38:49AM -0400, Vivien Didelot wrote:
> Only the 88E6185 family has bits 15:12 Cascade Port bits in the Global
> Control 2 register. Hence inconsistent values are actually written in
> this register for other families.
> 
> Add a .set_cascade_port operation to isolate the 88E6185 case, and call
> it from the device mapping setup function.
> 
> Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew