Received: by 10.192.165.148 with SMTP id m20csp296785imm; Wed, 9 May 2018 12:53:17 -0700 (PDT) X-Google-Smtp-Source: AB8JxZoifM7WdlaxdVzs1b8ZtG/wNm82svDr/7L/9LvHUPAtv+/OaXIgTCHGuB5/0bVLS1aD/cx7 X-Received: by 2002:a17:902:a716:: with SMTP id w22-v6mr11809954plq.215.1525895597525; Wed, 09 May 2018 12:53:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525895597; cv=none; d=google.com; s=arc-20160816; b=CPEwtethcq9zzL8oppB67rEzf/UQPElD/Vbn0k/J2BBSXPdw62d1zpUcrwfZEMJfSF rxN851vszc45U/zufleZMjWV+rlVRZJF0rSdaU1j4qMTQMAufmcpYECWW5L5qmbjuJXp 1cnI338EUxRkGhUsxu2NkuC78+dZWRTFGk8dt7Bto5CT6398gowlwRHYpVJmAbyghIjf UIzmTf8xmyFqOUbvF79G3/PpCkwKO3qe7UfCamwSfyYxotYtCU/B4T4X8GYhL9x3yY9v 7QnoVhyGFdQO3NQk+/8F/tAOyQIMOunQGfJbLDXGuS8W1DbyHlA6DTXPaM40Buc9L5+t Ot5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:dkim-signature :arc-authentication-results; bh=zJWqC86Fk9tUgflFjptBHMGtLbiHaoGf9h1PrjXyrhU=; b=UvWbI7VkQpcLjeuo1R3mN9/lsqB1ouEhdqTDqGX7m6SXgGvP3PvnfKKJ9eR3ZpS/vY XYYygavxJOkiSIBwDdkJ/R9c3SGlo0FCien8xl7FsCPTyIPtkWcespD+uG5qKjlQDK5l m9kzn1yH//3vHgQNqW7UgIp1jer2DW4fofD5KBkcqQ/jYo6tIvXFx+rvaxwPbCOFH8NF s9XRxnQLD95DSlevrWS5fr3dH36h4U5tnBrTXGjI1hKBBcYa4QXcmiRMLA2u6nWKFh4R f5Lfut/+I4Cn20kUS6RIpTFsJDvqIwY7GSyuYQtu/LaHGGDxvzesJXQC6x00XOOXB6zt hq0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=Z6uyR2zW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ba9-v6si26713734plb.110.2018.05.09.12.53.02; Wed, 09 May 2018 12:53:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=Z6uyR2zW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965925AbeEITvm (ORCPT + 99 others); Wed, 9 May 2018 15:51:42 -0400 Received: from mail.kernel.org ([198.145.29.99]:56766 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965532AbeEITvl (ORCPT ); Wed, 9 May 2018 15:51:41 -0400 Received: from mail-wr0-f176.google.com (mail-wr0-f176.google.com [209.85.128.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id E3E2A21852 for ; Wed, 9 May 2018 19:51:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1525895501; bh=iOM6mQHVC0Ul5b4EgBP0GcGEh4A9ncwOwYqh1hHj7X8=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=Z6uyR2zW8uJZ0TmvH5rOUEJCd0CB3YekfUyqqq/uyOxy2FKxS6g42khAE1Q5J+quC hnnbgq4pYDg42iBQEJ/Tw0mcRJN6rUluqbwbF9PvEQFOdrN9HJV9pJqnxkUV6fMkvV SBRrr3JdNl4f3x8mLl5yytmadKCmbePVnyGuS1y0= Received: by mail-wr0-f176.google.com with SMTP id v5-v6so36679169wrf.9 for ; Wed, 09 May 2018 12:51:40 -0700 (PDT) X-Gm-Message-State: ALQs6tCmcVc7LN+PBDfPVRtg5wT0hiNhjGAvJ3qJQ6meydxdjirlYrcY PnLdXHYvggLj3F3pTUmP8ZUHAq8X2MYYIr5qDp0fqg== X-Received: by 2002:adf:b456:: with SMTP id v22-v6mr26860043wrd.67.1525895499223; Wed, 09 May 2018 12:51:39 -0700 (PDT) MIME-Version: 1.0 References: <1525634395-23380-1-git-send-email-frederic@kernel.org> <1525634395-23380-5-git-send-email-frederic@kernel.org> <20180508111323.mmjo4ky4txzi4gx4@lakrids.cambridge.arm.com> <20180509113257.hl6frl424trdt2em@lakrids.cambridge.arm.com> In-Reply-To: <20180509113257.hl6frl424trdt2em@lakrids.cambridge.arm.com> From: Andy Lutomirski Date: Wed, 09 May 2018 19:51:28 +0000 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 4/9] arm: Split breakpoint validation into "check" and "commit" To: Mark Rutland Cc: Frederic Weisbecker , LKML , Jiri Olsa , Namhyung Kim , Peter Zijlstra , Linus Torvalds , Yoshinori Sato , Benjamin Herrenschmidt , Catalin Marinas , Chris Zankel , Paul Mackerras , Thomas Gleixner , Will Deacon , Michael Ellerman , Rich Felker , Ingo Molnar , Alexander Shishkin , Andrew Lutomirski , Arnaldo Carvalho de Melo , Max Filippov Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 9, 2018 at 4:33 AM Mark Rutland wrote: > On Tue, May 08, 2018 at 12:13:23PM +0100, Mark Rutland wrote: > > Hi Frederick, > > > > On Sun, May 06, 2018 at 09:19:50PM +0200, Frederic Weisbecker wrote: > > > The breakpoint code mixes up attribute check and commit into a single > > > code entity. Therefore the validation may return an error due to > > > incorrect atributes while still leaving halfway modified architecture > > > breakpoint struct. > > > > > > Prepare fox fixing this misdesign and separate both logics. > > > > Could you elaborate on what the problem is? I would have expected that > > when arch_build_bp_info() returns an error code, we wouldn't > > subsequently use the arch_hw_breakpoint information. Where does that > > happen? > From digging, I now see that this is a problem when > modify_user_hw_breakpoint() is called on an existing breakpoint. It > would be nice to mention that in the commit message. > > I also see that the check and commit hooks have to duplicate a > > reasonable amount of logic, e.g. the switch on bp->attr.type. Can we > > instead refactor the existing arch_build_bp_info() hooks to use a > > temporary arch_hw_breakpoint, and then struct assign it after all the > > error cases, > e.g. > > > > static int arch_build_bp_info(struct perf_event *bp) > > { > > struct arch_hw_breakpoint hbp; > > > > if (some_condition(bp)) > > hbp->field = 0xf00; > > > > switch (bp->attr.type) { > > case FOO: > > return -EINVAL; > > case BAR: > > hbp->other_field = 7; > > break; > > }; > > > > if (failure_case(foo)) > > return err; > > > > *counter_arch_bp(bp) = hbp; > > } > > > > ... or is that also problematic? > IIUC, this *would* work, but it is a little opaque. > Perhaps we could explicitly pass the temporary arch_hw_breakpoint in, > and have the core code struct-assign it after checking for errors? Hmm, maybe. OTOH, I'm not really convinced that arch_hw_breakpoint is even needed. x86 at least could probably just regenerate the DRn and DR7 bits on the fly as needed rather than caching them with basically no loss in performance. I completely agree that reducing duplication would be nice.