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[209.132.180.67]) by mx.google.com with ESMTP id v1-v6si634480pgr.30.2018.05.10.05.51.05; Thu, 10 May 2018 05:51:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935405AbeEJMux (ORCPT + 99 others); Thu, 10 May 2018 08:50:53 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:55496 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757217AbeEJMuw (ORCPT ); Thu, 10 May 2018 08:50:52 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7A7AD80D; Thu, 10 May 2018 05:50:51 -0700 (PDT) Received: from [10.1.210.88] (e110467-lin.cambridge.arm.com [10.1.210.88]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CE7123F592; Thu, 10 May 2018 05:50:48 -0700 (PDT) Subject: Re: [PATCH v1 3/5] arm64: dts: rockchip: Add gpio-syscon10 to rk3328 To: djw@t-chip.com.cn, linux-rockchip@lists.infradead.org Cc: Mark Rutland , devicetree@vger.kernel.org, Wayne Chou , Heiko Stuebner , Arnd Bergmann , Catalin Marinas , Will Deacon , linux-kernel@vger.kernel.org, Sugar Zhang , Rob Herring , Finley Xiao , David Wu , William Wu , Rocky Hao , linux-arm-kernel@lists.infradead.org References: <1525943800-14095-1-git-send-email-djw@t-chip.com.cn> <1525943800-14095-4-git-send-email-djw@t-chip.com.cn> From: Robin Murphy Message-ID: <76f2bbde-e158-a186-f136-9fb610a810c5@arm.com> Date: Thu, 10 May 2018 13:50:47 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <1525943800-14095-4-git-send-email-djw@t-chip.com.cn> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/05/18 10:16, djw@t-chip.com.cn wrote: > From: Levin Du > > Adding a new gpio controller named "gpio-syscon10" to rk3328, providing > access to the pins defined in the syscon GRF_SOC_CON10. This is the GPIO_MUTE pin, right? The public TRM is rather vague, but cross-referencing against the datasheet and schematics implies that it's the "gpiomut_*" part of the GRF bit names which is most significant. It might be worth using a more descriptive name here, since "syscon10" is pretty much meaningless at the board level. Robin. > Boards using these special pins to control regulators or LEDs, can now > utilize existing drivers like gpio-regulator and leds-gpio. > > Signed-off-by: Levin Du > > --- > > Changes in v1: > - Split from V0 and add to rk3328.dtsi for general use. > > arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi > index b8e9da1..73a822d 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi > @@ -309,6 +309,12 @@ > mode-loader = ; > }; > > + gpio_syscon10: gpio-syscon10 { > + compatible = "rockchip,gpio-syscon"; > + gpio-controller; > + #gpio-cells = <2>; > + gpio,syscon-dev = <0 0x0428 0>; > + }; > }; > > uart0: serial@ff110000 { >