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[209.132.180.67]) by mx.google.com with ESMTP id b12-v6si3647243plk.327.2018.05.11.08.54.43; Fri, 11 May 2018 08:54:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751438AbeEKPy0 (ORCPT + 99 others); Fri, 11 May 2018 11:54:26 -0400 Received: from bmailout2.hostsharing.net ([83.223.90.240]:60959 "EHLO bmailout2.hostsharing.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750711AbeEKPyY (ORCPT ); Fri, 11 May 2018 11:54:24 -0400 Received: from h08.hostsharing.net (h08.hostsharing.net [83.223.95.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "*.hostsharing.net", Issuer "COMODO RSA Domain Validation Secure Server CA" (not verified)) by bmailout2.hostsharing.net (Postfix) with ESMTPS id EF9E8280EEAEB; Fri, 11 May 2018 17:54:22 +0200 (CEST) Received: by h08.hostsharing.net (Postfix, from userid 100393) id 8769677805; Fri, 11 May 2018 17:54:22 +0200 (CEST) Date: Fri, 11 May 2018 17:54:22 +0200 From: Lukas Wunner To: poza@codeaurora.org Cc: Bjorn Helgaas , Philippe Ombredanne , Thomas Gleixner , Greg Kroah-Hartman , Kate Stewart , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Dongdong Liu , Keith Busch , Wei Zhang , Sinan Kaya , Timur Tabi Subject: Re: [PATCH v16 5/9] PCI/AER: Factor out error reporting from AER Message-ID: <20180511155422.GA333@wunner.de> References: <1526035408-31328-1-git-send-email-poza@codeaurora.org> <1526035408-31328-6-git-send-email-poza@codeaurora.org> <20180511125857.GA23225@wunner.de> <7317531a7a85404d590008a27131955f@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <7317531a7a85404d590008a27131955f@codeaurora.org> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, May 11, 2018 at 09:04:36PM +0530, poza@codeaurora.org wrote: > On 2018-05-11 18:28, Lukas Wunner wrote: > >On Fri, May 11, 2018 at 06:43:24AM -0400, Oza Pawandeep wrote: > >>+void pcie_do_fatal_recovery(struct pci_dev *dev) > >>+{ > >>+ struct pci_dev *udev; > >>+ struct pci_bus *parent; > >>+ struct pci_dev *pdev, *temp; > >>+ pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED; > >>+ struct aer_broadcast_data result_data; > >>+ > >>+ if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) > >>+ udev = dev; > >>+ else > >>+ udev = dev->bus->self; > >>+ > >>+ parent = udev->subordinate; > >>+ pci_lock_rescan_remove(); > >>+ list_for_each_entry_safe_reverse(pdev, temp, &parent->devices, > >>+ bus_list) { > >>+ pci_dev_get(pdev); > >>+ pci_dev_set_disconnected(pdev, NULL); > >>+ if (pci_has_subordinate(pdev)) > >>+ pci_walk_bus(pdev->subordinate, > >>+ pci_dev_set_disconnected, NULL); > >>+ pci_stop_and_remove_bus_device(pdev); > >>+ pci_dev_put(pdev); > >>+ } > > > >Any reason not to simply call > > > > pci_walk_bus(udev->subordinate, pci_dev_set_disconnected, NULL); > > > >before the list_for_each_entry_safe_reverse() iteration, instead of > >calling it for each device on the subordinate bus and for each > >device's children? Should be semantically identical, saves 3 LoC > >and saves wasted cycles of acquiring pci_bus_sem over and over again > >for each device on the subordinate bus. > > Well this is borrowed code from DPC driver, hence I thought to keep the > same. > but to me it looks like its taking care of PCIe switch where is goes through > all the subordinates, and which could turn out to be more swicthes down the > line, and son on... > it goes all the way down to the tree ... which is precisely what the one line I suggested above does. You don't need to respin for this alone as far as I'm concerned, but please post a follow-up refactoring patch. I have a patch in the pipeline which makes the same change in pciehp, hence this caught my eye. Thanks, Lukas