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Date:   Sun, 13 May 2018 01:03:53 -0700 (PDT)
From:   Liran Alon <liran.alon@oracle.com>
To:     <kernellwp@gmail.com>
Cc:     <rkrcmar@redhat.com>, <pbonzini@redhat.com>,
        <linux-kernel@vger.kernel.org>, <kvm@vger.kernel.org>,
        <junaids@google.com>
Subject: Re: [PATCH 2/2] KVM: X86: Fix loss of CR3_PCID_INVD bit when guest
 writes CR3
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----- kernellwp@gmail.com wrote:

> From: Wanpeng Li <wanpengli@tencent.com>
>=20
> SDM volume 3, section 4.10.4:
>=20
> * MOV to CR3. The behavior of the instruction depends on the value of
> CR4.PCIDE:
> =E2=80=94 If CR4.PCIDE =3D 1 and bit 63 of the instruction=E2=80=99s sour=
ce operand is
> 1, the=20
>   instruction is not required to invalidate any TLB entries or entries
> in=20
>   paging-structure caches.
>=20
> The CR3_PCID_INVD bit should not be removed if CR4.PCIDE =3D 1 when
> guest writes=20
> CR3, this patch fixes it.
>=20
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> Cc: Radim Kr=C4=8Dm=C3=A1=C5=99 <rkrcmar@redhat.com>
> Cc: Junaid Shahid <junaids@google.com>
> Signed-off-by: Wanpeng Li <wanpengli@tencent.com>
> ---
>  arch/x86/kvm/x86.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>=20
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> index 9a90668..438f140 100644
> --- a/arch/x86/kvm/x86.c
> +++ b/arch/x86/kvm/x86.c
> @@ -849,11 +849,13 @@ EXPORT_SYMBOL_GPL(kvm_set_cr4);
> =20
>  int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
>  {
> +=09unsigned long cr3_check =3D cr3;
> +
>  #ifdef CONFIG_X86_64
>  =09bool pcid_enabled =3D kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
> =20
>  =09if (pcid_enabled)
> -=09=09cr3 &=3D ~CR3_PCID_INVD;
> +=09=09cr3_check &=3D ~CR3_PCID_INVD;
>  #endif
> =20
>  =09if (cr3 =3D=3D kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
> @@ -863,7 +865,7 @@ int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned
> long cr3)
>  =09}
> =20
>  =09if (is_long_mode(vcpu) &&
> -=09    (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
> +=09    (cr3_check & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
>  =09=09return 1;
>  =09else if (is_pae(vcpu) && is_paging(vcpu) &&
>  =09=09   !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
> --=20
> 2.7.4

This commit doesn't seem correct to me.

According to Intel SDM "MOV=E2=80=94Move to/from Control Registers":
"If CR4.PCIDE =3D 1, bit 63 of the source operand to MOV to CR3 determines =
whether the instruction
invalidates entries in the TLBs and the paging-structure caches
(see Section 4.10.4.1, =E2=80=9COperations that Invalidate TLBs and Paging-=
Structure Caches,=E2=80=9D
in the Intel=C2=AE 64 and IA-32 Architectures Software Developer=E2=80=99s =
Manual, Volume 3A).
The instruction does not modify bit 63 of CR3, which is reserved and always=
 0."

However, after this commit kvm_set_cr3() will update vcpu->arch.cr3 to have=
 bit CR3_PCID_INVD set.
Which is wrong as it should be reserved and always 0.