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[209.132.180.67]) by mx.google.com with ESMTP id a2-v6si5634035pgu.26.2018.05.13.01.54.32; Sun, 13 May 2018 01:54:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=kH2bjz5v; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751406AbeEMIyW (ORCPT + 99 others); Sun, 13 May 2018 04:54:22 -0400 Received: from mail-oi0-f66.google.com ([209.85.218.66]:39632 "EHLO mail-oi0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750862AbeEMIyV (ORCPT ); Sun, 13 May 2018 04:54:21 -0400 Received: by mail-oi0-f66.google.com with SMTP id n65-v6so8194460oig.6; Sun, 13 May 2018 01:54:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=Z+8k/paOZVNZO3dmdYJw+8Wm1KIouoUYwfn1rfuK0tY=; b=kH2bjz5vmSOFV7xXcuhmBqDtQNgWzAkOGzDQOJgJ35kB3KeWx0ShhqCb4tMoZb1UrM wD7SEUadppxMi0i7boaSyRHCN1Fpbzmng7YGt6ONzyNArzn7lzpbI9S2SZQP4kZCjVkV rlDVY+ynhcU18ohBqvIsiiicY7J8fFFKyR0O07yjPhR4DP8bR+s5KKzzRRijiG89oO4i nMfB/xNT0oE0svxzAUCYKOnIgFBrQ9Ym/N+nddOVoz4RoAYy4X9SWSKGanBE9kFaltbq q4ZIldb6n7rYDMTtlKCcQw+jxHG/4toZ2ZRtTWXJj7nAS+Q8gTxvyJXGiCGvmpTs1VHG BzGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=Z+8k/paOZVNZO3dmdYJw+8Wm1KIouoUYwfn1rfuK0tY=; b=CgYajAq/hHif7vUFcv9V7cm772+txI1CfQROOMh+w10s0tBI9xhwYk3xUytCK+Gpop SoiWAWvoCQiCv+clPjsILU68dZFZtiysVISxP+ZNWDfduyiPznyVJLnT+A2IQlV8Ej// m4aaseQEoa/8Df4Uv80dNI9stm+a8nzWJVDyC5Cti64hfNBkTdsm6hYUdDYFYmLjDfPo GW2ea/fcz2eHEt8YkrocRKwld8dML2IkLH+GtUADmDeIMuV8xiiD2rxttnMTWcV+OhzP 7jTCfzLpSgFMAPmJszTKOdtwZvOJ0TJRDv2DdqZZ//0UQ9WsinmJPX/nTryXgrbSXWRh ceEw== X-Gm-Message-State: ALKqPwdoZo8q9oGhmDBXiE6A7mq7chzd0tQ7iImE/m59A6/RJpJ1PMWL BmgTUnEzad5wpw2NPM62CZtA5kiSECkaSMe6MsY= X-Received: by 2002:aca:b2c6:: with SMTP id b189-v6mr3796450oif.186.1526201660825; Sun, 13 May 2018 01:54:20 -0700 (PDT) MIME-Version: 1.0 Received: by 10.74.70.211 with HTTP; Sun, 13 May 2018 01:54:20 -0700 (PDT) In-Reply-To: <6c3c9a5b-ccf3-4702-8832-b44a98822966@default> References: <6c3c9a5b-ccf3-4702-8832-b44a98822966@default> From: Wanpeng Li Date: Sun, 13 May 2018 16:54:20 +0800 Message-ID: Subject: Re: [PATCH 1/2] KVM: X86: Fix CR3 reserve bits To: Liran Alon Cc: Radim Krcmar , Paolo Bonzini , LKML , Junaid Shahid , kvm Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 2018-05-13 16:28 GMT+08:00 Liran Alon : > > ----- kernellwp@gmail.com wrote: > >> 2018-05-13 15:53 GMT+08:00 Liran Alon : >> > >> > ----- kernellwp@gmail.com wrote: >> > >> >> From: Wanpeng Li >> >> >> >> MSB of CR3 is a reserved bit if the PCIDE bit is not set in CR4. >> >> It should be checked when PCIDE bit is not set, however commit >> >> 'd1cd3ce900441 ("KVM: MMU: check guest CR3 reserved bits based on >> >> its physical address width")' removes the bit 63 checking >> >> unconditionally. This patch fixes it by checking bit 63 of CR3 >> >> when PCIDE bit is not set in CR4. >> >> >> >> Fixes: d1cd3ce900441 (KVM: MMU: check guest CR3 reserved bits based >> on >> >> its physical address width) >> >> Cc: Paolo Bonzini >> >> Cc: Radim Kr=C4=8Dm=C3=A1=C5=99 >> >> Cc: Junaid Shahid >> >> Signed-off-by: Wanpeng Li >> >> --- >> >> arch/x86/kvm/emulate.c | 4 +++- >> >> arch/x86/kvm/x86.c | 2 +- >> >> 2 files changed, 4 insertions(+), 2 deletions(-) >> >> >> >> diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c >> >> index b3705ae..b21f427 100644 >> >> --- a/arch/x86/kvm/emulate.c >> >> +++ b/arch/x86/kvm/emulate.c >> >> @@ -4189,7 +4189,9 @@ static int check_cr_write(struct >> >> x86_emulate_ctxt *ctxt) >> >> maxphyaddr =3D eax & 0xff; >> >> else >> >> maxphyaddr =3D 36; >> >> - rsvd =3D rsvd_bits(maxphyaddr, 62); >> >> + if (ctxt->ops->get_cr(ctxt, 4) & >> X86_CR4_PCIDE) >> >> + new_val &=3D ~CR3_PCID_INVD; >> >> + rsvd =3D rsvd_bits(maxphyaddr, 63); >> > >> > I would prefer instead to do this: >> > if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PCIDE) >> > rsvd &=3D ~CR3_PCID_INVD; >> > It makes more sense as opposed to temporary removing the >> CR3_PCID_INVD bit from new_val. >> >> It tries the same way >> https://urldefense.proofpoint.com/v2/url?u=3Dhttps-3A__git.kernel.org_pu= b_scm_virt_kvm_kvm.git_commit_-3Fid-3Dc19986fea873f3c745122bf79013a872a190f= 212&d=3DDwIFaQ&c=3DRoP1YumCXCgaWHvlZYR8PZh8Bv7qIrMUB65eapI_JnE&r=3DJk6Q8nNz= kQ6LJ6g42qARkg6ryIDGQr-yKXPNGZbpTx0&m=3Dr52WDgKBorUHwe_B_5Nw2Le_F_E0ne8lqqW= W6n-3bSg&s=3DufTcXvhhAMkY3XP6gAx-HiKCT8ynPWo2fs2z9DqCzM4&e=3D >> pointed out. >> >> Regards, >> Wanpeng Li > > Yes but there it makes sense as new CR3 value should not have bit 63 set = in vcpu->arch.cr3. When X86_CR4_PCIDE =3D=3D 0 and CR3 63 bit is set, a #GP is missing in your suggestion. Regards, Wanpeng Li