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From:   Hao Zhang <hao5781286@gmail.com>
Date:   Tue, 15 May 2018 00:08:57 +0800
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Subject: Re: [linux-sunxi] [PATCH v2 2/4] ARM: dtsi: add pwm node for sun8i.
To:     =?UTF-8?Q?Andr=C3=A9_Przywara?= <andre.przywara@arm.com>
Cc:     Thierry Reding <thierry.reding@gmail.com>, robh+dt@kernel.org,
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        Chen-Yu Tsai <wens@csie.org>,
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        open list <linux-kernel@vger.kernel.org>,
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2018-02-28 9:53 GMT+08:00 Andr=C3=A9 Przywara <andre.przywara@arm.com>:
> Hi,
>
> The subject line should mention the R40, there are far too many sun8i SoC=
s.

Okey.

>
> On 25/02/18 13:51, hao_zhang wrote:
>> This patch adds pwm node for sun8i.
>>
>> Signed-off-by: hao_zhang <hao5781286@gmail.com>
>> ---
>>  arch/arm/boot/dts/sun8i-r40.dtsi | 13 +++++++++++++
>>  1 file changed, 13 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-=
r40.dtsi
>> index 173dcc1..99a0261 100644
>> --- a/arch/arm/boot/dts/sun8i-r40.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
>> @@ -295,6 +295,11 @@
>>                               bias-pull-up;
>>                       };
>>
>> +                     pwm_ch0_pin: pwm-ch0-pin {
>> +                             pins =3D "PB2";
>> +                             function =3D "pwm";
>> +                     };
>> +
>>                       uart0_pb_pins: uart0-pb-pins {
>>                               pins =3D "PB22", "PB23";
>>                               function =3D "uart0";
>> @@ -306,6 +311,14 @@
>>                       reg =3D <0x01c20c90 0x10>;
>>               };
>>
>> +             pwm: pwm@1c23400 {
>> +                          compatible =3D "allwinner,sun8i-r40-pwm";
>> +                          reg =3D <0x01c23400 0x154>;
>
> Following my comments on the binding document:
>                         interrupts =3D <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
>
>> +                          clocks =3D <&osc24M>;
>
> And possibly multiple clocks here (though I fail to find the APB1 clock
> being exposed by our CCU).

It seem CCU dosen't support APB1 clock for R40 PWM...

>
> Cheers,
> Andre.
>
>> +                          #pwm-cells =3D <3>;
>> +                          status =3D "disabled";
>> +             };
>> +
>>               uart0: serial@1c28000 {
>>                       compatible =3D "snps,dw-apb-uart";
>>                       reg =3D <0x01c28000 0x400>;
>>
>