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[209.132.180.67]) by mx.google.com with ESMTP id r4-v6si8065001pgt.613.2018.05.14.15.10.24; Mon, 14 May 2018 15:10:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=NcXpsdZb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752155AbeENWKI (ORCPT + 99 others); Mon, 14 May 2018 18:10:08 -0400 Received: from mail.kernel.org ([198.145.29.99]:36930 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751978AbeENWKG (ORCPT ); Mon, 14 May 2018 18:10:06 -0400 Received: from localhost (unknown [104.132.1.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 8E2F921726; Mon, 14 May 2018 22:10:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1526335805; bh=r+Lz2F+1xZ5mXDz4RNIK1f2MSqL3q+i4GzJqF5Km6Cw=; h=To:From:In-Reply-To:Cc:References:Subject:Date:From; b=NcXpsdZbaVpRzubM+Sme2Q4S8JhFCkGfe+HdiOEUfI+dnwpYJPz1VadtAY1DLJ69m SlK6kb38wZlJGBt8sAxY4mqckGbOjFhdyEJ3frLLnKDziOZJXeAgC1nPZeqs7Pe9o3 2yd1bN32c21Wxaqyh4tkYiWva6i58RKhBZrqe0j0= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: "moderated list:ARM64 PORT AARCH64 ARCHITECTURE" , "open list:ARM/QUALCOMM SUPPORT" , "open list:ARM/QUALCOMM SUPPORT" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Andy Gross , Catalin Marinas , David Brown , Mark Rutland , Rob Herring , Will Deacon , Yossi Mansharoff , open list From: Stephen Boyd In-Reply-To: <1523973390-2387-1-git-send-email-yossim@codeaurora.org> Cc: Yossi Mansharoff References: <1523973390-2387-1-git-send-email-yossim@codeaurora.org> Message-ID: <152633580491.34267.3508281594437081335@swboyd.mtv.corp.google.com> User-Agent: alot/0.7 Subject: Re: [PATCH v2] arm64: dts: qcom: Collapse usb support into one node Date: Mon, 14 May 2018 15:10:04 -0700 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Quoting Yossi Mansharoff (2018-04-17 06:56:30) > We currently have three device nodes for the same USB hardware > block, as evident by the reuse of the same reg address multiple > times. Now that the chipidea driver fully supports OTG with the > MSM wrapper we can collapse all these nodes into one USB device > node, reflecting the true nature of the hardware. None of this makes sense. Commit text is totally bogus now. > = > diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/= dts/qcom/apq8016-sbc.dtsi > index 9ff8487..1505921 100644 > --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi > +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi > @@ -371,18 +372,18 @@ > adp-disable; > hnp-disable; > srp-disable; > - dr_mode =3D "host"; > - pinctrl-names =3D "default"; > - pinctrl-0 =3D <&usb_sw_sel_pm>; > + mux-controls =3D <&usb_switch>; > + mux-control-names =3D "usb_switch"; > + > ulpi { > phy { > v1p8-supply =3D <&pm8916_l7>; > v3p3-supply =3D <&pm8916_l13>; > - extcon =3D <&usb_id>; > }; > }; > }; > = > + Why the newline? > lpass@7708000 { > status =3D "okay"; > }; > @@ -512,11 +513,17 @@ > = > usb_id: usb-id { > compatible =3D "linux,extcon-usb-gpio"; > - vbus-gpio =3D <&msmgpio 121 GPIO_ACTIVE_HIGH>; > + id-gpio =3D <&msmgpio 121 GPIO_ACTIVE_HIGH>; Hmm? > pinctrl-names =3D "default"; > pinctrl-0 =3D <&usb_id_default>; > }; > = > + usb_switch: usb-switch { > + compatible =3D "gpio-mux"; Needs a better compatible string for the actual mux part. The gpio-mux can come after that because it's generic, but it's good to record the actual mux part too. > + mux-gpios =3D <&pm8916_gpios 4 GPIO_ACTIVE_HIGH>; > + #mux-control-cells =3D <0>; > + };