Received: by 2002:ac0:a594:0:0:0:0:0 with SMTP id m20-v6csp693504imm; Tue, 15 May 2018 07:50:10 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpRl3jc9dkKNDp90Z72zYqPIo0M7oAPas6icQfg77b1l5tSbDZkPA15mUHWywGaef42Q3cH X-Received: by 2002:a62:104a:: with SMTP id y71-v6mr15265711pfi.188.1526395810831; Tue, 15 May 2018 07:50:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526395810; cv=none; d=google.com; s=arc-20160816; b=iPIirIEAmdO4wliyvLbkG/zZVTroPvhrAabL0niOeWXQxSRbgPoduVvzdDhcZy+nI5 LuHwiRb0GoU3FFmecWsNLmyVQWxfDNGkGSLrOfbu+ovmePEnURIf6OUiAtLzjUNRjCwy i0J6woav5ajY+dEkqmHr65F5gVWE4W6PZrGgXciQKt4MjNN2ZZH6VZAA//lkyFMdAEHH LvG93xNiXFKZXqwKiDJmfYQx9Y/rVyGc+lc/WnNu1OEHkHA8V7CknuqNJJT8Jy++DCBs RBcrrveVnLDEQBwSdddNkDEijD/eE/TrrWZgtDP1/WMV1OIgAj2usE2Ahf0gUs2sCQ0r ZHTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=JqqRhFE/5ydmlcHrGLQHQBK9S73HdYlo3DUPud2UgkE=; b=R7kM8NtdDTvuLmCpLZUtryEhR8R53xcY2iEvidK8mQPnW4IvHxgqjOPqhkm/QxEukU grU2OlWEMqQn5Ik6xCikFDRvKJRIt2Bk/EZY5u/TiUIwMiAvnX+xcNjRp8YY0oR24yfc +gXCEtvNGCpsjD53eROXv+Iu17oN8ijjQ+1CrKM0p3Xx2e/LeIbuwVw2IeOJ9xEA0Ajf NIt932u4Z4MgVG7xCSJKvFZAA+CJ8vrVsQ2+4xMoLwGG8Eop1sfVhCdYPlflK2C9EAqU 8OqUWbG86CNV4iIYyKrj1ILJwhLYmhokwC8eMvmvHCxPGUoi08D3SB+ZTm3h8Jhp0jHy O/Ow== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o9-v6si141980pgp.508.2018.05.15.07.49.53; Tue, 15 May 2018 07:50:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753718AbeEOOoe (ORCPT + 99 others); Tue, 15 May 2018 10:44:34 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.150.225]:55938 "EHLO 9pmail.ess.barracuda.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752145AbeEOOoa (ORCPT ); Tue, 15 May 2018 10:44:30 -0400 Received: from MIPSMAIL01.mipstec.com (mailrelay.mips.com [12.201.5.28]) by mx3.ess.sfj.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NO); Tue, 15 May 2018 14:43:58 +0000 Received: from mredfearn-linux.mipstec.com (192.168.155.41) by MIPSMAIL01.mipstec.com (10.20.43.31) with Microsoft SMTP Server (TLS) id 14.3.361.1; Tue, 15 May 2018 07:44:26 -0700 From: Matt Redfearn To: Florian Fainelli , James Hogan , Ralf Baechle CC: , Matt Redfearn , Namhyung Kim , "Maciej W. Rozycki" , Peter Zijlstra , , Paul Burton , Ingo Molnar , Jiri Olsa , Alexander Shishkin , Arnaldo Carvalho de Melo Subject: [PATCH v4] MIPS: perf: Fix BMIPS5000 system mode counting Date: Tue, 15 May 2018 15:44:16 +0100 Message-ID: <1526395456-23723-1-git-send-email-matt.redfearn@mips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1524219789-31241-8-git-send-email-matt.redfearn@mips.com> References: <1524219789-31241-8-git-send-email-matt.redfearn@mips.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [192.168.155.41] X-BESS-ID: 1526395437-298554-23259-46541-1 X-BESS-VER: 2018.6-r1805102334 X-BESS-Apparent-Source-IP: 12.201.5.28 X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.193012 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When perf is used in system mode, i.e. specifying a set of CPUs to count (perf -a -C cpu), event->cpu is set to the CPU number on which events should be counted. The current BMIPS500 variation of mipsxx_pmu_enable_event only over sets the counter to count the current CPU, so system mode does not work. Fix this by removing this BMIPS5000 specific path and integrating it with the generic one. Since BMIPS5000 uses specific extensions to the perf control register, different fields must be set up to count the relevant CPU. Signed-off-by: Matt Redfearn Tested-by: Florian Fainelli --- Changes in v4: Fix compiler error from BRCM_PERFCTRL_VPEID flagged by Florian. Changes in v2: New patch to fix BMIPS5000 system mode perf. arch/mips/include/asm/mipsregs.h | 1 + arch/mips/kernel/perf_event_mipsxx.c | 17 ++++++----------- 2 files changed, 7 insertions(+), 11 deletions(-) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index a4baaaa02bc..6b0b06d2683 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -735,6 +735,7 @@ #define MIPS_PERFCTRL_MT_EN_TC (_ULCAST_(2) << 20) /* PerfCnt control register MT extensions used by BMIPS5000 */ +#define BRCM_PERFCTRL_VPEID(v) (_ULCAST_(1) << (12 + (v))) #define BRCM_PERFCTRL_TC (_ULCAST_(1) << 30) /* PerfCnt control register MT extensions used by Netlogic XLR */ diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 5b8811643e6..77d7167e303 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -364,16 +364,7 @@ static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx) /* Make sure interrupt enabled. */ MIPS_PERFCTRL_IE; -#ifdef CONFIG_CPU_BMIPS5000 - { - /* enable the counter for the calling thread */ - unsigned int vpe_id; - - vpe_id = smp_processor_id() & MIPS_CPUID_TO_COUNTER_MASK; - cpuc->saved_ctrl[idx] |= BIT(12 + vpe_id) | BRCM_PERFCTRL_TC; - } -#else -#ifdef CONFIG_MIPS_MT_SMP +#if defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_CPU_BMIPS5000) if (range > V) { /* The counter is processor wide. Set it up to count all TCs. */ pr_debug("Enabling perf counter for all TCs\n"); @@ -390,12 +381,16 @@ static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx) */ cpu = (event->cpu >= 0) ? event->cpu : smp_processor_id(); +#if defined(CONFIG_CPU_BMIPS5000) + ctrl = BRCM_PERFCTRL_VPEID(cpu & MIPS_CPUID_TO_COUNTER_MASK); + ctrl |= BRCM_PERFCTRL_TC; +#else ctrl = M_PERFCTL_VPEID(cpu_vpe_id(&cpu_data[cpu])); ctrl |= M_TC_EN_VPE; +#endif cpuc->saved_ctrl[idx] |= ctrl; pr_debug("Enabling perf counter for CPU%d\n", cpu); } -#endif /* CONFIG_CPU_BMIPS5000 */ /* * We do not actually let the counter run. Leave it until start(). */ -- 2.7.4