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[209.132.180.67]) by mx.google.com with ESMTP id s12-v6si357255pgq.616.2018.05.15.10.17.12; Tue, 15 May 2018 10:17:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754258AbeEORRE (ORCPT + 99 others); Tue, 15 May 2018 13:17:04 -0400 Received: from muru.com ([72.249.23.125]:42176 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753575AbeEORRD (ORCPT ); Tue, 15 May 2018 13:17:03 -0400 Received: from atomide.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id 26B2180BD; Tue, 15 May 2018 17:19:09 +0000 (UTC) Date: Tue, 15 May 2018 10:16:59 -0700 From: Tony Lindgren To: Faiz Abbas Cc: linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, devicetree@vger.kernel.org, bcousson@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com, paul@pwsan.com, lokeshvutla@ti.com, linux@armlinux.org.uk, Tero Kristo Subject: Re: [PATCH 2/3] ARM: dts: dra762: Add MCAN clock support Message-ID: <20180515171659.GQ98604@atomide.com> References: <1523181542-3770-1-git-send-email-faiz_abbas@ti.com> <1523181542-3770-3-git-send-email-faiz_abbas@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1523181542-3770-3-git-send-email-faiz_abbas@ti.com> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Faiz Abbas [180408 09:59]: > From: Lokesh Vutla > > MCAN is clocked by H14 divider of DPLL_GMAC. Unlike other > DPLL dividers this DPLL_GMAC H14 divider is controlled by > control module. Adding support for these clocks. Adding Tero to Cc on this one. > Signed-off-by: Lokesh Vutla > Signed-off-by: Faiz Abbas > --- > arch/arm/boot/dts/dra76x.dtsi | 33 +++++++++++++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > > diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi > index 1c88c58..bfc8263 100644 > --- a/arch/arm/boot/dts/dra76x.dtsi > +++ b/arch/arm/boot/dts/dra76x.dtsi > @@ -17,3 +17,36 @@ > &crossbar_mpu { > ti,irqs-skip = <10 67 68 133 139 140>; > }; > + > +&scm_conf_clocks { > + dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc { > + #clock-cells = <0>; > + compatible = "ti,divider-clock"; > + clocks = <&dpll_gmac_x2_ck>; > + ti,max-div = <63>; > + reg = <0x03fc>; > + ti,bit-shift=<20>; > + ti,latch-bit=<26>; > + assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>; > + assigned-clock-rates = <80000000>; > + }; > + > + dpll_gmac_h14x2_ctrl_mux_ck: dpll_gmac_h14x2_ctrl_mux_ck@3fc { > + #clock-cells = <0>; > + compatible = "ti,mux-clock"; > + clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>; > + reg = <0x3fc>; > + ti,bit-shift = <29>; > + ti,latch-bit=<26>; > + assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; > + assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>; > + }; > + > + mcan_clk: mcan_clk@3fc { > + #clock-cells = <0>; > + compatible = "ti,gate-clock"; > + clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; > + ti,bit-shift = <27>; > + reg = <0x3fc>; > + }; > +}; > -- > 2.7.4 >