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[209.132.180.67]) by mx.google.com with ESMTP id y25-v6si1712401pfn.248.2018.05.15.21.32.35; Tue, 15 May 2018 21:32:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=WPegw3U1; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752061AbeEPEbp (ORCPT + 99 others); Wed, 16 May 2018 00:31:45 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:51919 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751859AbeEPEbn (ORCPT ); Wed, 16 May 2018 00:31:43 -0400 Received: by mail-wm0-f66.google.com with SMTP id j4-v6so4499198wme.1; Tue, 15 May 2018 21:31:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=etns7icVONVnXw6cNPZQTLCr+Tmhk9uoslMjoMI8yF8=; b=WPegw3U1uIl30MKWeOsF1AdgsR10qPa+j3Rvx3yp4oBoC/0evLWISQDOIgtEwiLY/e kFh0fJHpgw61/ljtO9iC/minYgoD6H8tRfizeqddhUw3ZTHZXUuESnpPIK283VxJrnIN hEurLGoTqyDajKqGigUzfUxc5MY+zEMtd6cNJNWbsbPAd4NNbwZkch3tLWWj4Dmv3kki sMBG9tb567W8m7N926H0jQfs2aAxnMy+TCaL3ZYQqzktAAEGTLMFK26SzJLRO2w/cHNu +xxiIMQCEm4Dq975GrPhP+RqPueo2usMvPUhZM4e8LiwoTbo7LlSTAXg0laGrIBeiFPo Kqrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=etns7icVONVnXw6cNPZQTLCr+Tmhk9uoslMjoMI8yF8=; b=hrpwgHzpJi5RuZtQikhIlUSp6RKvXd8cpvYi9/2Wak5Nxo0Zw+WkRcgisK4hkW6ZnD mkngWz8Aj65XFUsZGy0kxyaDG1WVlC0GiC67C78/AdWMTzn+1OdaclevkpGVoD9J+Ow3 wAO0wSHlp5UwERRS94qfoUaCepeYgKjj8lT3NKFtO8MYSdp3fynWJbooCSjmoM3AkeDM drUCXtKCun9adPGOe0cMlq6SEQQ/yUoBA5Wb5/zPjtdiNF2tBTR1tWQyNy19L2RR0948 OvIo+UkuvJ0VcHU0H3G+yhCstP5mRPZEiqz9Yk0MKL0et4cNmFV3ZmbXLHQ68TMWYtNv ol5w== X-Gm-Message-State: ALKqPwfGC9Y8JX/iLfcMo3njkljdJ09CLIw4L8F6CTyXHIcVJ/lhq1sB 8+MlRD9rCRnvIXrvqyYF/Z/6Mbii+mUATBGlV9U= X-Received: by 2002:a50:a4f6:: with SMTP id x51-v6mr20941887edb.247.1526445101594; Tue, 15 May 2018 21:31:41 -0700 (PDT) MIME-Version: 1.0 Received: by 10.80.247.66 with HTTP; Tue, 15 May 2018 21:31:01 -0700 (PDT) In-Reply-To: <1520507013-2410-1-git-send-email-alim.akhtar@samsung.com> References: <1520507013-2410-1-git-send-email-alim.akhtar@samsung.com> From: Alim Akhtar Date: Wed, 16 May 2018 10:01:01 +0530 Message-ID: Subject: Re: [RFC PATCH V2] scsi: ufs: Add specific callback for setting DMA mask To: Alim Akhtar Cc: linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org, jejb@linux.vnet.ibm.com, martin.petersen@oracle.com, vinayak holikatti , subhashj@codeaurora.org, devicetree@vger.kernel.org, Shaik Ameer Basha Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Ping !!! On Thu, Mar 8, 2018 at 4:33 PM, Alim Akhtar wrote: > Currently DMA mask for UFS HCI is set by reading CAP register's > [64AS] bit. Some HCI controller like Exynos support 36-bit bus address. > This works perfectly fine with DMA mask set as 64 in case there is no > IOMMU attached to HCI. > In case if HCI is behind an IOMMU, setting DMA mask as 64 bit won't > work as HCI has only 36bit addressing and SMMU has created mapping of > 64 bit and as the device truncates the address, its mapping will not > be found by iommu. > To resolve such issues, let the variant driver sets its own DMA mask. > > Signed-off-by: Alim Akhtar > --- > drivers/scsi/ufs/ufshcd.c | 3 +++ > drivers/scsi/ufs/ufshcd.h | 2 ++ > 2 files changed, 5 insertions(+) > > I am not sure if there are other ways available to handle such cases. > The IOMMU I am talking about is arm-smmu and it DT binding does not > give much idea about handling such cases. > Have tested this patch with HCI controller with IOMMU attached. > > Changes Since V1: > - Fixed build issue as reported by Kbuild test robot. > > diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c > index a355d98..9a1374e 100644 > --- a/drivers/scsi/ufs/ufshcd.c > +++ b/drivers/scsi/ufs/ufshcd.c > @@ -7781,6 +7781,9 @@ EXPORT_SYMBOL_GPL(ufshcd_dealloc_host); > */ > static int ufshcd_set_dma_mask(struct ufs_hba *hba) > { > + if (hba->vops && hba->vops->set_dma_mask) > + return hba->vops->set_dma_mask(hba); > + > if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) { > if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64))) > return 0; > diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h > index 1332e54..89c6dae 100644 > --- a/drivers/scsi/ufs/ufshcd.h > +++ b/drivers/scsi/ufs/ufshcd.h > @@ -297,6 +297,7 @@ struct ufs_pwr_mode_info { > * @resume: called during host controller PM callback > * @dbg_register_dump: used to dump controller debug information > * @phy_initialization: used to initialize phys > + * @set_dma_mask: used to set variant specific DMA mask > */ > struct ufs_hba_variant_ops { > const char *name; > @@ -325,6 +326,7 @@ struct ufs_hba_variant_ops { > int (*resume)(struct ufs_hba *, enum ufs_pm_op); > void (*dbg_register_dump)(struct ufs_hba *hba); > int (*phy_initialization)(struct ufs_hba *); > + int (*set_dma_mask)(struct ufs_hba *hba); > }; > > /* clock gating state */ > -- > 2.7.4 > -- Regards, Alim