Received: by 2002:ac0:a594:0:0:0:0:0 with SMTP id m20-v6csp1766184imm; Wed, 16 May 2018 02:45:10 -0700 (PDT) X-Google-Smtp-Source: AB8JxZoAoTaPOUrzhmIJotuyAR3CSaxOTtRQYQauUAz8DgxVwMWG57ieIL7KFQN9Wek//6maUEiN X-Received: by 2002:a17:902:24a5:: with SMTP id w34-v6mr200542pla.52.1526463910071; Wed, 16 May 2018 02:45:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526463910; cv=none; d=google.com; s=arc-20160816; b=nz4+mM5t6VVujDbwRjJdf4QiHkHGedAw8yXdHWvLM0duwlwakhND5giYXNVypr14Zg lxq6K8qSnsqLDJxNxX3G6or3FTNG+4jtpsNUqzpN6ssJu1EzyQORZDlkfqgmnUlsCSxo y70ingOJdRux+3JXDP9W5eWhJewOpcXkOeso8UXj+eYaT3gqa32RGO/tnwYzAUN3tVN1 bdK7rJji08OoHMdTr086E8EJXWy8dbrDfFRKDt744BMaWL5EHujnI8WVTt3xZy9rPduB fpzq6P40hAXq+EkeGpA2DmMVnDKCo8mJaBkmq3ugQ/jSocDfRcDRih6y7o9NywiLz9ps AVqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :dlp-reaction:dlp-version:dlp-product:content-language :accept-language:in-reply-to:references:message-id:date:thread-index :thread-topic:subject:cc:to:from:arc-authentication-results; bh=ZMP1aBRDCTQDUvxOyB69zEPuhgFSskDTCwYaj0+FYfA=; b=ovxlmLj525W1o8iAVZy8g/XpdiG/YfDwOQseM4nVJSiaroWn8Un485c+FdSxyfPNd5 UmrSRB4SaYBQzTqZAWHIcWFJuq/290uBjyn5r6Q9T6WqTqgVmAT0Kd4n1C3kRWgkyl3V UnHJU7pv0LIGnS+Qd+wVryJ1Arq6Wk6i+Mb1B1zXEUwF0xJn30iVYPL65XHbUqBMNi8V gBaILzDWN7KezLSVfJy6rzsRVPI5xe832gkOKpjQraSuPxllRw7UfQ7bLRA5Xa6MkOM9 2l5L1XcoYEo610+jPWQtp/+TAHGWIs5D0KJhyrixP5IDQvQiU2a+AqHzDUkh8pUrXU9a 3uzQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f19-v6si1439629pgn.460.2018.05.16.02.44.55; Wed, 16 May 2018 02:45:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752389AbeEPJnE convert rfc822-to-8bit (ORCPT + 99 others); Wed, 16 May 2018 05:43:04 -0400 Received: from mga05.intel.com ([192.55.52.43]:4720 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751664AbeEPJnC (ORCPT ); Wed, 16 May 2018 05:43:02 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 May 2018 02:43:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,390,1520924400"; d="scan'208";a="39746658" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga007.fm.intel.com with ESMTP; 16 May 2018 02:43:01 -0700 Received: from fmsmsx112.amr.corp.intel.com (10.18.116.6) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 16 May 2018 02:43:01 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by FMSMSX112.amr.corp.intel.com (10.18.116.6) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 16 May 2018 02:43:00 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.40]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.179]) with mapi id 14.03.0319.002; Wed, 16 May 2018 17:42:59 +0800 From: "Kang, Luwei" To: Alexander Shishkin CC: "kvm@vger.kernel.org" , "tglx@linutronix.de" , "mingo@redhat.com" , "hpa@zytor.com" , "x86@kernel.org" , "chao.p.peng@linux.intel.com" , "thomas.lendacky@amd.com" , "bp@suse.de" , "Liang, Kan" , "Janakarajan.Natarajan@amd.com" , "dwmw@amazon.co.uk" , "linux-kernel@vger.kernel.org" , "peterz@infradead.org" , "mathieu.poirier@linaro.org" , "kstewart@linuxfoundation.org" , "gregkh@linuxfoundation.org" , "pbonzini@redhat.com" , "rkrcmar@redhat.com" , "david@redhat.com" , "bsd@redhat.com" , "yu.c.zhang@linux.intel.com" , "joro@8bytes.org" Subject: RE: [PATCH v8 01/12] perf/x86/intel/pt: Move Intel-PT MSRs bit definitions to a public header Thread-Topic: [PATCH v8 01/12] perf/x86/intel/pt: Move Intel-PT MSRs bit definitions to a public header Thread-Index: AQHT62JliC5AtH9UP0+sBA4842ekgqQuffyAgAOeMWA= Date: Wed, 16 May 2018 09:42:58 +0000 Message-ID: <82D7661F83C1A047AF7DC287873BF1E167F7B1B8@SHSMSX101.ccr.corp.intel.com> References: <1526295432-20640-1-git-send-email-luwei.kang@intel.com> <1526295432-20640-2-git-send-email-luwei.kang@intel.com> <20180514102217.uc3kzhu6gs4wapuo@um.fi.intel.com> In-Reply-To: <20180514102217.uc3kzhu6gs4wapuo@um.fi.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZWRiZDRmOWItMjlkMS00MThmLWEwMGUtNWY5NTBhMTQxODRkIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiJNcUY2V09uXC9IQVNaYnBwa3dlT1ZESUU2d1wvWGY1U04wK0NTT3lwOGJaZ2VGM3F1VTd3NjhIYVFmOFNoSWRxV0IifQ== dlp-product: dlpe-windows dlp-version: 11.0.200.100 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > > From: Chao Peng > > > > Intel Processor Trace virtualization enabling in KVM guest need to > > access these MSRs bit definitions, so move them to public header file > > msr-index.h. > > @@ -115,6 +148,7 @@ > > #define MSR_IA32_RTIT_ADDR2_B 0x00000585 > > #define MSR_IA32_RTIT_ADDR3_A 0x00000586 > > #define MSR_IA32_RTIT_ADDR3_B 0x00000587 > > +#define MSR_IA32_RTIT_ADDR_RANGE 4 > > This one wasn't there before, so belongs in a different patch. What about move this definition to "arch/x86/include/asm/intel_pt.h " and be added in patch 8 (implementation of context switch). Thanks, Luwei Kang > > Regards, > -- > Alex