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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: 0568bd35-b193-4622-086b-08d5bb2979d4 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0568bd35-b193-4622-086b-08d5bb2979d4 X-MS-Exchange-CrossTenant-originalarrivaltime: 16 May 2018 12:35:15.2373 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0201MB1924 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, As per NVME specification:=20 7.5.1.1 Host Software Interrupt Handling It is recommended that host software utilize the Interrupt Mask Set and Int= errupt Mask Clear (INTMS/INTMC)=20 registers to efficiently handle interrupts when configured to use pin based= or MSI messages. In kernel 4.14, drivers/nvme/host/pci.c function nvme_isr=20 doesn't use these registers.=20 Any reason why these registers are not used in nvme interrupt handler ? Why NVMe driver is not using any bottom half and processing all completion = queues in interrupt handler ? Regards, Bharat