Received: by 2002:ac0:a594:0:0:0:0:0 with SMTP id m20-v6csp1987744imm; Wed, 16 May 2018 06:16:19 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpVHLjuv1+jEAjIdNCM76NxHnR8I13PPHefg/AUQ2jiyXqGuE7yS1KEuXB5IduVuiIdl3Do X-Received: by 2002:a62:3bcb:: with SMTP id w72-v6mr930929pfj.129.1526476579815; Wed, 16 May 2018 06:16:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526476579; cv=none; d=google.com; s=arc-20160816; b=QDUoRv85sekJKSVCmqT7RbpstueNzF2ffeYiWkhn47fafFnu51XPX0B08VUTqOrGzZ 3z8rpbQSAPFtjJ9yrrW3g/kRZcv7Zz9dK1IlyjbEwpCwlbhUPyVBNLFx7GFqLqQTxbvB JEjbFERgB+bblii+jacg9Exb3HbgCP0pkwoI6jgufCYZ73WDchWWWLoEn03tO8eYSPx9 2AokymWLxFbnatcD5PAxNtGKN9OybZlFvxRrn/+HJ/jVe46lY07evBB0PzNf49EkalYA 9NqrvoZQV244PXLsJD3kUb0a8tNEzTDVMfcQsSq41H7xyoPsEfDKV/Ow8latUW67xT1B NZKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:cc:to:subject:message-id:date:from :references:in-reply-to:mime-version:dkim-signature:dkim-signature :arc-authentication-results; bh=WtwBTP7ybhvAIf5YY3wBTtzVrVilt1m537DFSZkALhs=; b=LijBR1yTcwVzEp6ctvzgq7LJOhTeBBrOjpjCYJ/vL1J6koIASQyn3TeTjApoq13ARc 6420V95LV/8Q/Yw2A2pZaOnlDSgIS7BKexLObG52SWLar79o6ODSUhXgobP79I6DgHDw hintAnAmiGnF+VUcleeYnFvQdv+kp3mahUs66tPn6y0ec9sVGIF7mxgx0qTla+rvRPMg bBI32Q3bRFRWvymYd/kwW8+kIsmf6MZvk/nvXq0YmMnYHBBDdShzpUXAnHzIwRU0g6tq O9ktSoPny4fZj7ZchbDsvW17shyaovPlg5bzFDX0zE5u4GO9MvM9JgsSPHqbeUkf2GOx GNvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@verdurent-com.20150623.gappssmtp.com header.s=20150623 header.b=xa3ZlM8g; dkim=fail header.i=@linaro.org header.s=google header.b=Oi1PRcC8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u8-v6si2106988pgv.277.2018.05.16.06.16.01; Wed, 16 May 2018 06:16:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@verdurent-com.20150623.gappssmtp.com header.s=20150623 header.b=xa3ZlM8g; dkim=fail header.i=@linaro.org header.s=google header.b=Oi1PRcC8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752657AbeEPNMd (ORCPT + 99 others); Wed, 16 May 2018 09:12:33 -0400 Received: from mail-ot0-f194.google.com ([74.125.82.194]:42873 "EHLO mail-ot0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752525AbeEPNM3 (ORCPT ); Wed, 16 May 2018 09:12:29 -0400 Received: by mail-ot0-f194.google.com with SMTP id l13-v6so809176otk.9 for ; Wed, 16 May 2018 06:12:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=verdurent-com.20150623.gappssmtp.com; s=20150623; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=WtwBTP7ybhvAIf5YY3wBTtzVrVilt1m537DFSZkALhs=; b=xa3ZlM8gkt/p69UPTievIwP/BDPOIFkSoPwVRm6ty8Pr22SS0RVEKOScLOf/+31S2z Gh7FKExN9Neyq2N5LjPI5bujav+3hFGE/t2cn6IFjMaRmCKpEohB+J0SLZUc+CzvFXAz tBEfRIIfjwL2JDr1WKY4NQ/1tlKlWFtkQBFNDF/juA2K48wGoKgbelpluVaOSEeVB9eX KlunZozM1tmHJ4731lfr+V351pG4gg0Mip5gVLts3efGnq8/xz7d2SILiTcq8DlpgWMr rL1pmMsGJzd1ChuCvndbT7pevXUU8AruBAo1EA7tHWqYh+eGXTars5IcYD3Jd7vk0pPk YM/w== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=WtwBTP7ybhvAIf5YY3wBTtzVrVilt1m537DFSZkALhs=; b=Oi1PRcC8OCLCCXaZnbO0bkDvZlK05xlRZE2jpr5gO7hqCdeHiZzPKH5ELd3CfqAR8h ASjRTMG9TuVKNOmlPOVfgQZAj06xNkuJI+2z6TsQhYS0AGolzOUuRmXGY5OdQVhmJZ/x 7p9bzbirgalsGRTkMFomdwaCUejDJkuTtM2II= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=WtwBTP7ybhvAIf5YY3wBTtzVrVilt1m537DFSZkALhs=; b=ZqrWoTkx6hPP69x3MoQY1VINBGocVjNYTee040CNgZuqpPEZ0eydaDU9kbNhsMc/Ap A4Jp2lSaKR7jN7yp51YpUflirCPG7PruK3+LSlpB7XioowOUrBH9P7VNLUt4dhUPRPkh i0r22/N5+NK3g2T3hymL+vu222xktvmS4O9hIpsvuFYYSfJw86ets2yOugwxdY+aXIZI wrbv5K8zIi6vl7y+BLRQrZkl71psmd/4m0/C8tIq6gAA1xWPM2fZYvXkncU3q8Z6e1/R huXJ8BC0sCeelEJncxKSVp736lJNfD+biHRjgd0fB8otCrbKujLWTMgt2AGRqV2GUwoW gBjA== X-Gm-Message-State: ALKqPwfe+iRgGxS+IaGwwTSKIqiis/CQuKvkH9P8TYHrQG66yU5u1Fh6 K4sDy868+Yqd9nkqWhB2wffmqo0Fzu8vWFziBtQIjQ== X-Received: by 2002:a9d:e8f:: with SMTP id 15-v6mr693369otj.14.1526476348471; Wed, 16 May 2018 06:12:28 -0700 (PDT) MIME-Version: 1.0 Received: by 10.74.196.133 with HTTP; Wed, 16 May 2018 06:12:27 -0700 (PDT) In-Reply-To: <1526375616-16904-14-git-send-email-ilialin@codeaurora.org> References: <1526375616-16904-1-git-send-email-ilialin@codeaurora.org> <1526375616-16904-14-git-send-email-ilialin@codeaurora.org> From: Amit Kucheria Date: Wed, 16 May 2018 16:12:27 +0300 X-Google-Sender-Auth: _yXxTM_y2fvatDkcQvpitrXndQo Message-ID: Subject: Re: [PATCH v7 13/14] dt-bindings: cpufreq: Document operating-points-v2-kryo-cpu To: Ilia Lin Cc: Michael Turquette , sboyd@kernel.org, Rob Herring , Mark Rutland , Viresh Kumar , nm@ti.com, lgirdwood@gmail.com, broonie@kernel.org, Andy Gross , David Brown , catalin.marinas@arm.com, will.deacon@arm.com, "Rafael J. Wysocki" , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, LKML , Linux PM list , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, lakml , Rajendra Nayak , nicolas.dechesne@linaro.org, celster@codeaurora.org, tfinkel@codeaurora.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, May 15, 2018 at 12:13 PM, Ilia Lin wrote: > In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996 > that have KRYO processors, the CPU ferequencies subset and voltage value s/ferequencies/frequency > of each OPP varies based on the silicon variant in use. > Qualcomm Technologies, Inc. Process Voltage Scaling Tables > defines the voltage and frequency value based on the msm-id in SMEM > and speedbin blown in the efuse combination. > The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC > to provide the OPP framework with required information. > This is used to determine the voltage and frequency value for each OPP of > operating-points-v2 table when it is parsed by the OPP framework. > > This change adds documentation. Change this to actually document the extension of the op-v2 binding with a list of compatible HW. > Signed-off-by: Ilia Lin > Acked-by: Viresh Kumar > --- > .../devicetree/bindings/opp/kryo-cpufreq.txt | 680 +++++++++++++++++++++ > 1 file changed, 680 insertions(+) > create mode 100644 Documentation/devicetree/bindings/opp/kryo-cpufreq.txt > > diff --git a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt b/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt > new file mode 100644 > index 0000000..c2127b9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt > @@ -0,0 +1,680 @@ > +Qualcomm Technologies, Inc. KRYO CPUFreq and OPP bindings > +=================================== > + > +In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996 > +that have KRYO processors, the CPU ferequencies subset and voltage value > +of each OPP varies based on the silicon variant in use. > +Qualcomm Technologies, Inc. Process Voltage Scaling Tables > +defines the voltage and frequency value based on the msm-id in SMEM > +and speedbin blown in the efuse combination. > +The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC > +to provide the OPP framework with required information (existing HW bitmap). > +This is used to determine the voltage and frequency value for each OPP of > +operating-points-v2 table when it is parsed by the OPP framework. > + > +Required properties: > +-------------------- > +In 'cpus' nodes: > +- operating-points-v2: Phandle to the operating-points-v2 table to use. > + > +In 'operating-points-v2' table: > +- compatible: Should be > + - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996. > +- nvmem-cells: A phandle pointing to a nvmem-cells node representing the > + efuse registers that has information about the > + speedbin that is used to select the right frequency/voltage > + value pair. > + Please refer the for nvmem-cells > + bindings Documentation/devicetree/bindings/nvmem/nvmem.txt > + and also examples below. > + > +In every OPP node: > +- opp-supported-hw: A single 32 bit bitmap value, representing compatible HW. > + Bitmap: > + 0: MSM8996 V3, speedbin 0 > + 1: MSM8996 V3, speedbin 1 > + 2: MSM8996 V3, speedbin 2 > + 3: unused > + 4: MSM8996 SG, speedbin 0 > + 5: MSM8996 SG, speedbin 1 > + 6: MSM8996 SG, speedbin 2 > + 7-31: unused > + > +Example 1: > +--------- > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + CPU0: cpu@0 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + clocks = <&kryocc 0>; > + cpu-supply = <&pm8994_s11_saw>; > + operating-points-v2 = <&cluster0_opp>; > + #cooling-cells = <2>; > + next-level-cache = <&L2_0>; > + L2_0: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + }; > + }; > + > + CPU1: cpu@1 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x1>; > + enable-method = "psci"; > + clocks = <&kryocc 0>; > + cpu-supply = <&pm8994_s11_saw>; > + operating-points-v2 = <&cluster0_opp>; > + #cooling-cells = <2>; > + next-level-cache = <&L2_0>; > + }; > + > + CPU2: cpu@100 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x100>; > + enable-method = "psci"; > + clocks = <&kryocc 1>; > + cpu-supply = <&pm8994_s11_saw>; > + operating-points-v2 = <&cluster1_opp>; > + #cooling-cells = <2>; > + next-level-cache = <&L2_1>; > + L2_1: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + }; > + }; > + > + CPU3: cpu@101 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x101>; > + enable-method = "psci"; > + clocks = <&kryocc 1>; > + cpu-supply = <&pm8994_s11_saw>; > + operating-points-v2 = <&cluster1_opp>; > + #cooling-cells = <2>; > + next-level-cache = <&L2_1>; > + }; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&CPU0>; > + }; > + > + core1 { > + cpu = <&CPU1>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&CPU2>; > + }; > + > + core1 { > + cpu = <&CPU3>; > + }; > + }; > + }; > + }; > + > + cluster0_opp: opp_table0 { > + compatible = "operating-points-v2-kryo-cpu"; > + nvmem-cells = <&speedbin_efuse>; > + opp-shared; > + > + opp-307200000 { > + opp-hz = /bits/ 64 <307200000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-384000000 { > + opp-hz = /bits/ 64 <384000000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-422400000 { > + opp-hz = /bits/ 64 <422400000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-460800000 { > + opp-hz = /bits/ 64 <460800000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-480000000 { > + opp-hz = /bits/ 64 <480000000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-537600000 { > + opp-hz = /bits/ 64 <537600000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-556800000 { > + opp-hz = /bits/ 64 <556800000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-614400000 { > + opp-hz = /bits/ 64 <614400000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-652800000 { > + opp-hz = /bits/ 64 <652800000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-691200000 { > + opp-hz = /bits/ 64 <691200000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-729600000 { > + opp-hz = /bits/ 64 <729600000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-768000000 { > + opp-hz = /bits/ 64 <768000000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-844800000 { > + opp-hz = /bits/ 64 <844800000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-902400000 { > + opp-hz = /bits/ 64 <902400000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-960000000 { > + opp-hz = /bits/ 64 <960000000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-979200000 { > + opp-hz = /bits/ 64 <979200000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-1036800000 { > + opp-hz = /bits/ 64 <1036800000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1056000000 { > + opp-hz = /bits/ 64 <1056000000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-1113600000 { > + opp-hz = /bits/ 64 <1113600000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1132800000 { > + opp-hz = /bits/ 64 <1132800000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-1190400000 { > + opp-hz = /bits/ 64 <1190400000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1209600000 { > + opp-hz = /bits/ 64 <1209600000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-1228800000 { > + opp-hz = /bits/ 64 <1228800000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1286400000 { > + opp-hz = /bits/ 64 <1286400000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-1324800000 { > + opp-hz = /bits/ 64 <1324800000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x5>; > + clock-latency-ns = <200000>; > + }; > + opp-1363200000 { > + opp-hz = /bits/ 64 <1363200000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x72>; > + clock-latency-ns = <200000>; > + }; > + opp-1401600000 { > + opp-hz = /bits/ 64 <1401600000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x5>; > + clock-latency-ns = <200000>; > + }; > + opp-1440000000 { > + opp-hz = /bits/ 64 <1440000000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-1478400000 { > + opp-hz = /bits/ 64 <1478400000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x1>; > + clock-latency-ns = <200000>; > + }; > + opp-1497600000 { > + opp-hz = /bits/ 64 <1497600000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x4>; > + clock-latency-ns = <200000>; > + }; > + opp-1516800000 { > + opp-hz = /bits/ 64 <1516800000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-1593600000 { > + opp-hz = /bits/ 64 <1593600000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x71>; > + clock-latency-ns = <200000>; > + }; > + opp-1996800000 { > + opp-hz = /bits/ 64 <1996800000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x20>; > + clock-latency-ns = <200000>; > + }; > + opp-2188800000 { > + opp-hz = /bits/ 64 <2188800000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x10>; > + clock-latency-ns = <200000>; > + }; > + }; > + > + cluster1_opp: opp_table1 { > + compatible = "operating-points-v2-kryo-cpu"; > + nvmem-cells = <&speedbin_efuse>; > + opp-shared; > + > + opp-307200000 { > + opp-hz = /bits/ 64 <307200000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-384000000 { > + opp-hz = /bits/ 64 <384000000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-403200000 { > + opp-hz = /bits/ 64 <403200000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-460800000 { > + opp-hz = /bits/ 64 <460800000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-480000000 { > + opp-hz = /bits/ 64 <480000000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-537600000 { > + opp-hz = /bits/ 64 <537600000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-556800000 { > + opp-hz = /bits/ 64 <556800000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-614400000 { > + opp-hz = /bits/ 64 <614400000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-652800000 { > + opp-hz = /bits/ 64 <652800000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-691200000 { > + opp-hz = /bits/ 64 <691200000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-729600000 { > + opp-hz = /bits/ 64 <729600000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-748800000 { > + opp-hz = /bits/ 64 <748800000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-806400000 { > + opp-hz = /bits/ 64 <806400000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-825600000 { > + opp-hz = /bits/ 64 <825600000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-883200000 { > + opp-hz = /bits/ 64 <883200000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-902400000 { > + opp-hz = /bits/ 64 <902400000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-940800000 { > + opp-hz = /bits/ 64 <940800000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-979200000 { > + opp-hz = /bits/ 64 <979200000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-1036800000 { > + opp-hz = /bits/ 64 <1036800000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1056000000 { > + opp-hz = /bits/ 64 <1056000000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-1113600000 { > + opp-hz = /bits/ 64 <1113600000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1132800000 { > + opp-hz = /bits/ 64 <1132800000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-1190400000 { > + opp-hz = /bits/ 64 <1190400000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1209600000 { > + opp-hz = /bits/ 64 <1209600000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-1248000000 { > + opp-hz = /bits/ 64 <1248000000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1286400000 { > + opp-hz = /bits/ 64 <1286400000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-1324800000 { > + opp-hz = /bits/ 64 <1324800000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1363200000 { > + opp-hz = /bits/ 64 <1363200000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-1401600000 { > + opp-hz = /bits/ 64 <1401600000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1440000000 { > + opp-hz = /bits/ 64 <1440000000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-1478400000 { > + opp-hz = /bits/ 64 <1478400000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1516800000 { > + opp-hz = /bits/ 64 <1516800000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-1555200000 { > + opp-hz = /bits/ 64 <1555200000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1593600000 { > + opp-hz = /bits/ 64 <1593600000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-1632000000 { > + opp-hz = /bits/ 64 <1632000000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1670400000 { > + opp-hz = /bits/ 64 <1670400000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-1708800000 { > + opp-hz = /bits/ 64 <1708800000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1747200000 { > + opp-hz = /bits/ 64 <1747200000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x70>; > + clock-latency-ns = <200000>; > + }; > + opp-1785600000 { > + opp-hz = /bits/ 64 <1785600000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1804800000 { > + opp-hz = /bits/ 64 <1804800000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x6>; > + clock-latency-ns = <200000>; > + }; > + opp-1824000000 { > + opp-hz = /bits/ 64 <1824000000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x71>; > + clock-latency-ns = <200000>; > + }; > + opp-1900800000 { > + opp-hz = /bits/ 64 <1900800000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x74>; > + clock-latency-ns = <200000>; > + }; > + opp-1920000000 { > + opp-hz = /bits/ 64 <1920000000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x1>; > + clock-latency-ns = <200000>; > + }; > + opp-1977600000 { > + opp-hz = /bits/ 64 <1977600000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x30>; > + clock-latency-ns = <200000>; > + }; > + opp-1996800000 { > + opp-hz = /bits/ 64 <1996800000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x1>; > + clock-latency-ns = <200000>; > + }; > + opp-2054400000 { > + opp-hz = /bits/ 64 <2054400000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x30>; > + clock-latency-ns = <200000>; > + }; > + opp-2073600000 { > + opp-hz = /bits/ 64 <2073600000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x1>; > + clock-latency-ns = <200000>; > + }; > + opp-2150400000 { > + opp-hz = /bits/ 64 <2150400000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x31>; > + clock-latency-ns = <200000>; > + }; > + opp-2246400000 { > + opp-hz = /bits/ 64 <2246400000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x10>; > + clock-latency-ns = <200000>; > + }; > + opp-2342400000 { > + opp-hz = /bits/ 64 <2342400000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x10>; > + clock-latency-ns = <200000>; > + }; > + }; > + > +.... > + > +reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > +.... > + smem_mem: smem-mem@86000000 { > + reg = <0x0 0x86000000 0x0 0x200000>; > + no-map; > + }; > +.... > +}; > + > +smem { > + compatible = "qcom,smem"; > + memory-region = <&smem_mem>; > + hwlocks = <&tcsr_mutex 3>; > +}; > + > +soc { > +.... > + qfprom: qfprom@74000 { > + compatible = "qcom,qfprom"; > + reg = <0x00074000 0x8ff>; > + #address-cells = <1>; > + #size-cells = <1>; > + .... > + speedbin_efuse: speedbin@133 { > + reg = <0x133 0x1>; > + bits = <5 3>; > + }; > + }; > +}; > -- > 1.9.1 >