Received: by 2002:ac0:a594:0:0:0:0:0 with SMTP id m20-v6csp2310452imm; Wed, 16 May 2018 10:52:56 -0700 (PDT) X-Google-Smtp-Source: AB8JxZojfrfkySXfKUijbzLhhnWCcK/PPJNzugPKr/f2A124JC0foel737snMBPXjBwWmyuy8e4R X-Received: by 2002:a62:dc4e:: with SMTP id t75-v6mr1910261pfg.139.1526493175959; Wed, 16 May 2018 10:52:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526493175; cv=none; d=google.com; s=arc-20160816; b=QpteSzW6bSSEP9GXd/w8ojRrxR2jYfoO6gnr9o9oWWsPbQ+gb5ugohWExqhiqHW9h6 BP0umZVYfjcPe5GeVGmaDkcHtOhTzkeG+mBOwkuio6wKlH5rGtr5k/1pZAidgQeA0uvB 4sgbuPpGjCKqz0rw8/scervO60kGHtUcNlBfDW4Ite7tjWNHvbH8t5pyW5GAgylLwnlG twy5lzxNyo7XS9ojcAYjmbZbM5ujILqQwEY+x6hO6XVXqV49Ec+8xWFe9IdlaKYGk0Ka 7DUYGJ42hiCSoAX4vC6R9egVDJ8BED+yKUSztAbCyYmOYtFWeUWc67Q6ZhGV7z1B3Tv3 B+cQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=UnpcblY91fwi06ZQzea3dG/BYp8xan+NU3z/6Idzi9o=; b=Y73RAE/K+HcyLcdkLb+PiKP7XGlNvr70yEebbsY9oTcEC4Mk7KYodYH0TWvLTJ/HhK /ssTEM1TPnZWXPNSwrbSjVQm9+lRlSe6C1Lik+HD0nXSGusw18y0LDgTmhHzcF2wb2rg lX8NGrHQSYUq2aBJTPtHF5hWrbUSgpPCmKYnEW8nCVa3/6gk02QH5lzrFR2Ze3/K+LOI E6/5xjuhF5+CtPzIjkDFAV0YAZGf0e5XXDj3dvG5j8dNZYkDfx4yYi6zXNuBCGI3X4vr 2rjkOFqVT0/xKWm/8vZYwnwHMM4g6+GLGrWkyJ+i1nydDxnHr0seZ5Roug+uKs6YzJ2+ obYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=k0dD9Qff; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 24-v6si3124712pfr.242.2018.05.16.10.52.41; Wed, 16 May 2018 10:52:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=k0dD9Qff; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752290AbeEPRwE (ORCPT + 99 others); Wed, 16 May 2018 13:52:04 -0400 Received: from mail-yb0-f194.google.com ([209.85.213.194]:40799 "EHLO mail-yb0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752267AbeEPRwC (ORCPT ); Wed, 16 May 2018 13:52:02 -0400 Received: by mail-yb0-f194.google.com with SMTP id o80-v6so555173ybc.7; Wed, 16 May 2018 10:52:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UnpcblY91fwi06ZQzea3dG/BYp8xan+NU3z/6Idzi9o=; b=k0dD9QffjqHrAN5Fr806E/kTTUOPrJBW93TLqexWXrga5V8zcVlDw0MnjnZEoF6KjK HFB50qbp9HsGC4oARwdr5GB5knQJjZHRGFjbTkx1H13SqHvyFuENt9jbZFUi4jKjqJy7 UFVbopXy3N1wMpz/xeXu60aUw97VynyvWZW9LKpt0rjGGNlYrqnkt91p8FLs9KGf+EDd kIVcYarPiAowOcXF03p7q27H1Gywnn2zT/rmxrs6FyxbpG61bl+Qm5m0pfuEBXpIQV65 ZQASxdBO+HGns1lUYpkBfqfomPrCTO7fJ7cxjMNt4Q1kCt50o+/HkE/nijTThMlgU7ml NNmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UnpcblY91fwi06ZQzea3dG/BYp8xan+NU3z/6Idzi9o=; b=FUByiKBzrzl6jU04y3p/S9XRuwq6wedY6+/zMhJTfB05QWJ4D84xePb5d+Oc8a2GXJ WzH6wYWdYjPyIcWrVB6z3nYYsXvKnikJ/83XsfbJ8fAt6oAS1+TAF7nhBTFKlYRWQZf3 mD7axazOo/BcRR6ODeWFLCoSj/go5U4nfLMpRUfhjMMnqfHT3mol4AMprYQVCv2w+7An O0/m4jxC8N9JRlUunow6YV71nhjMFBnaOPZsJnmzoU2WxBQAoFypCfAErzd92HBn695f yMjFG4T7YJ7DAdjfMNWLHjRKIRiF5UHx9hEQv4rXDmTfLdekhJUjpQKN7HWRrtST0hu5 UoJQ== X-Gm-Message-State: ALKqPwelYvnxqM5t3vtAgn5ciFh1zHjdiQxx25qfmudyiHzw95va+niO msJfIq3K6PuEkEtFhabbPCE= X-Received: by 2002:a25:e08:: with SMTP id 8-v6mr1080743ybo.71.1526493121644; Wed, 16 May 2018 10:52:01 -0700 (PDT) Received: from localhost ([72.188.97.40]) by smtp.gmail.com with ESMTPSA id r12-v6sm1088714ywl.59.2018.05.16.10.52.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 May 2018 10:52:01 -0700 (PDT) From: William Breathitt Gray To: jic23@kernel.org Cc: benjamin.gaignard@st.com, fabrice.gasnier@st.com, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Rob Herring , Mark Rutland , William Breathitt Gray Subject: [PATCH v6 6/9] dt-bindings: counter: Document stm32 quadrature encoder Date: Wed, 16 May 2018 13:51:55 -0400 Message-Id: X-Mailer: git-send-email 2.17.0 In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Benjamin Gaignard Add bindings for STM32 Timer quadrature encoder. It is a sub-node of STM32 Timer which implement the counter part of the hardware. Cc: Rob Herring Cc: Mark Rutland Signed-off-by: Benjamin Gaignard Signed-off-by: William Breathitt Gray --- .../bindings/counter/stm32-timer-cnt.txt | 26 +++++++++++++++++++ .../devicetree/bindings/mfd/stm32-timers.txt | 7 +++++ 2 files changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt diff --git a/Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt b/Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt new file mode 100644 index 000000000000..377728128bef --- /dev/null +++ b/Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt @@ -0,0 +1,26 @@ +STMicroelectronics STM32 Timer quadrature encoder + +STM32 Timer provides quadrature encoder counter mode to detect +angular position and direction of rotary elements, +from IN1 and IN2 input signals. + +Must be a sub-node of an STM32 Timer device tree node. +See ../mfd/stm32-timers.txt for details about the parent node. + +Required properties: +- compatible: Must be "st,stm32-timer-counter". +- pinctrl-names: Set to "default". +- pinctrl-0: List of phandles pointing to pin configuration nodes, + to set IN1/IN2 pins in mode of operation for Low-Power + Timer input on external pin. + +Example: + timers@40010000 { + compatible = "st,stm32-timers"; + ... + counter { + compatible = "st,stm32-timer-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&tim1_in_pins>; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/stm32-timers.txt b/Documentation/devicetree/bindings/mfd/stm32-timers.txt index 1db6e0057a63..ff9c14ada30b 100644 --- a/Documentation/devicetree/bindings/mfd/stm32-timers.txt +++ b/Documentation/devicetree/bindings/mfd/stm32-timers.txt @@ -23,6 +23,7 @@ Optional parameters: Optional subnodes: - pwm: See ../pwm/pwm-stm32.txt - timer: See ../iio/timer/stm32-timer-trigger.txt +- counter: See ../counter/stm32-timer-cnt.txt Example: timers@40010000 { @@ -43,4 +44,10 @@ Example: compatible = "st,stm32-timer-trigger"; reg = <0>; }; + + counter { + compatible = "st,stm32-timer-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&tim1_in_pins>; + }; }; -- 2.17.0