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[209.132.180.67]) by mx.google.com with ESMTP id 7-v6si4748301pff.154.2018.05.16.23.25.44; Wed, 16 May 2018 23:25:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EHZrEAxd; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752343AbeEQGZH (ORCPT + 99 others); Thu, 17 May 2018 02:25:07 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:50869 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752211AbeEQGZD (ORCPT ); Thu, 17 May 2018 02:25:03 -0400 Received: by mail-wm0-f66.google.com with SMTP id t11-v6so6380768wmt.0 for ; Wed, 16 May 2018 23:25:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to :user-agent; bh=hB/8FaZWZNr/JY3JWLA6zJmhXq/8/a/ITGASK8ti/Hw=; b=EHZrEAxdDEP9nMGdBa9hX3xT0ERjBsko75QZUa4V71NmxYnu5lnjhLq9WUuVXlTSJd 6H01CoyiaPepsanPYn0owAtNlo1Ld43/pfMVGr5dEvZP+0dLGIu4JAGj3uizoSnW7b+3 hCXRCIP19n5AauGpw44BPZXqsSgvUl7prknSA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to:user-agent; bh=hB/8FaZWZNr/JY3JWLA6zJmhXq/8/a/ITGASK8ti/Hw=; b=rP9wjMIQ7gSgK4lnCo0uptum6szuOlvTJ3wzkkEOdQ/7dTNaIjORnyaqxADMrKlROX hn2CCvVOv7yPztAOa8cznhpVrMe6xTxNXV8QccHM/If3UVHHn6DVnmxhAk3IpP350gCV phah+g3EWtAJt9qXfgcq4c61mBiMsgwbAugwSKAAdNA+QMx3lH8cMBOcccQqanAB9FDe OS82q2P0QM+IgnJfPBMzYSVPS+Q4zcb3RmPBq6mSzcayTqaWweo47f79XjJ6RlSpCbPd G2LHM03+xyg56djLk4lqkh43l1MrG78vfhYM58paP3pWzl9GKeE1xKkbozaQ32YZprFx E3Zw== X-Gm-Message-State: ALKqPwfBS52IgnvvISK3PYkb32EYixQYh6kmoOz8QcI3UpOJnC07f6k2 VMTvghjroE9yDBcTT7h6zgF2IA== X-Received: by 2002:a1c:e156:: with SMTP id y83-v6mr790386wmg.92.1526538302404; Wed, 16 May 2018 23:25:02 -0700 (PDT) Received: from dell ([2.31.167.140]) by smtp.gmail.com with ESMTPSA id y68-v6sm8756858wrb.91.2018.05.16.23.25.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 23:25:01 -0700 (PDT) Date: Thu, 17 May 2018 07:25:00 +0100 From: Lee Jones To: Hoan Tran Cc: Phil Edworthy , Andy Shevchenko , Hoan Tran , Linus Walleij , Mark Rutland , Rob Herring , Michel Pollet , "linux-gpio@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-renesas-soc@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v6] gpio: dwapb: Add support for 1 interrupt per port A GPIO Message-ID: <20180517062500.GJ5130@dell> References: <1526027497-32556-1-git-send-email-phil.edworthy@renesas.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 16 May 2018, Hoan Tran wrote: > Hi Phil, > > On 5/11/18, 1:31 AM, "Phil Edworthy" wrote: > > The DesignWare GPIO IP can be configured for either 1 interrupt or 1 > per GPIO in port A, but the driver currently only supports 1 interrupt. > See the DesignWare DW_apb_gpio Databook description of the > 'GPIO_INTR_IO' parameter. > > This change allows the driver to work with up to 32 interrupts, it will > get as many interrupts as specified in the DT 'interrupts' property. > It doesn't do anything clever with the different interrupts, it just calls > the same handler used for single interrupt hardware. > > Signed-off-by: Phil Edworthy > Reviewed-by: Rob Herring > Acked-by: Lee Jones > --- > One point to mention is that I have made it possible for users to have > unconnected interrupts by specifying holes in the list of interrupts. This is > done by supporting the interrupts-extended DT prop. > However, I have no use for this and had to hack some test case for this. > Perhaps the driver should support 1 interrupt or all GPIOa as interrupts? > > v6: > - Treat DT and ACPI the same as much as possible. Note that we can't use > platform_get_irq() to get the DT interrupts as they are in the port > sub-node and hence do not have an associated platform device. > v5: > - Rolled ACPI companion code provided by Hoan Tran into this patch. > v4: > - Use of_irq_get() instead of of_irq_parse_one()+irq_create_of_mapping() > v3: > - Rolled mfd: intel_quark_i2c_gpio fix into this patch to avoid bisect problems > v2: > - Replaced interrupt-mask DT prop with support for the interrupts-extended > prop. This means replacing the call to irq_of_parse_and_map() with calls > to of_irq_parse_one() and irq_create_of_mapping(). > --- > .../devicetree/bindings/gpio/snps-dwapb-gpio.txt | 9 +++- > drivers/gpio/gpio-dwapb.c | 49 +++++++++++++++------- > drivers/mfd/intel_quark_i2c_gpio.c | 3 +- > include/linux/platform_data/gpio-dwapb.h | 3 +- > 4 files changed, 45 insertions(+), 19 deletions(-) > > diff --git a/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt b/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt > index 4a75da7..3c1118b 100644 > --- a/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt > +++ b/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt > @@ -26,8 +26,13 @@ controller. > the second encodes the triger flags encoded as described in > Documentation/devicetree/bindings/interrupt-controller/interrupts.txt > - interrupt-parent : The parent interrupt controller. > -- interrupts : The interrupt to the parent controller raised when GPIOs > - generate the interrupts. > +- interrupts : The interrupts to the parent controller raised when GPIOs > + generate the interrupts. If the controller provides one combined interrupt > + for all GPIOs, specify a single interrupt. If the controller provides one > + interrupt for each GPIO, provide a list of interrupts that correspond to each > + of the GPIO pins. When specifying multiple interrupts, if any are unconnected, > + use the interrupts-extended property to specify the interrupts and set the > + interrupt controller handle for unused interrupts to 0. > - snps,nr-gpios : The number of pins in the port, a single cell. > - resets : Reset line for the controller. > > Acked-by: Hoan Tran Well that's new. I've never seen a mailer reply like that before. Which mailer are you using? Might be worth sorting that out. -- Lee Jones [李琼斯] Linaro Services Technical Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog