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[209.132.180.67]) by mx.google.com with ESMTP id y34-v6si4699814plb.17.2018.05.17.02.06.56; Thu, 17 May 2018 02:07:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@endlessm-com.20150623.gappssmtp.com header.s=20150623 header.b=rFOwLH5i; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752280AbeEQJFn (ORCPT + 99 others); Thu, 17 May 2018 05:05:43 -0400 Received: from mail-wm0-f67.google.com ([74.125.82.67]:52269 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751980AbeEQJFk (ORCPT ); Thu, 17 May 2018 05:05:40 -0400 Received: by mail-wm0-f67.google.com with SMTP id w194-v6so7029837wmf.2 for ; Thu, 17 May 2018 02:05:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=endlessm-com.20150623.gappssmtp.com; s=20150623; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=gxpjw/ogz3dBB9Gksdrk96hq7fo0vDdnK5abSrtt7kM=; b=rFOwLH5iIHfP2Qu6/Sfe7wlpK+BBAfgMCJYZVbJh9ZxFVsFiDJjxDqhqabQG7y9C1O JQn1xZSDw0Vf3PcuEORy3nGvyGIpVu543UjttbiR6m3VjCaQzKqZR1Zip54+y/GCoPN8 sad1uqedtbO4rIv2RN9RAOK5TIUt7TvnAFeRfnAJpDoqu4H41Xc9v0Rp8Qw5MmEs6CuI nx/Gw0DNcQCgOGIWW/JQLyjt70w+OquBsJtD2NRPm5uagOkQpPkFpr+rgp3U64LowUlC xO506wjcW489dmQ+i6PsAFnf06GcCp1cWvSbgiSFWNoItiac5APZjFL+yV2MdXQ95tin RrEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=gxpjw/ogz3dBB9Gksdrk96hq7fo0vDdnK5abSrtt7kM=; b=TCCdKmPuMKHtYHXf8p9tnLKwfK3iboe4zJDhm5Fz3mde8bBp4fS2J7Ot0weLI3Tn4v E7N2I1JwnAl+QNtL9YZ5798cdcROAyTjTvaAxuuwV7cVHYWx5qShAvqD0db/cj6JtrrS XP4fRUrHAoPAETZ291aZ0H6HqU5LWkiqM4DGTHsDYTG4nBn0WD1G4JKTbI2z7bzXDG6h pJrDvxjKH0artoFHjZX5AF9DLDNOd+gIDrMAeEfnwt65yOn9G4ANIP01DXjkF6OuepRH rYPOBmFL3I4PzukC0QoQcP+ocgHZKKpF5fSEHc5zHNb/Q2RV+/bSozg10B0VZLrOhecx rrqw== X-Gm-Message-State: ALKqPwf5pI5NhEpNLE56p4Oy1thdEacxf+fLavl/It/xqah1R2JsHaI3 sW5tq0tLcukgYR/GJnAnz/qbNHUygLP6dHiI9Ucwog== X-Received: by 2002:a50:f4b5:: with SMTP id s50-v6mr5857051edm.262.1526547938922; Thu, 17 May 2018 02:05:38 -0700 (PDT) MIME-Version: 1.0 Received: by 10.80.245.113 with HTTP; Thu, 17 May 2018 02:05:38 -0700 (PDT) In-Reply-To: References: <7728da79-8a7a-b87d-d09c-b36978b3032e@linux.intel.com> From: Chris Chiu Date: Thu, 17 May 2018 17:05:38 +0800 Message-ID: Subject: Re: [BUG] i2c-hid: ELAN Touchpad does not work on ASUS X580GD To: Jarkko Nikula Cc: Daniel Drake , Jian-Hong Pan , Jiri Kosina , Benjamin Tissoires , Jani Nikula , Hans de Goede , Dmitry Torokhov , Adrian Salido , Jason Gerecke , linux-input , Andy Shevchenko , Mika Westerberg , Wolfram Sang , linux-i2c@vger.kernel.org, Linux Kernel , Linux Upstreaming Team Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, May 17, 2018 at 3:48 PM, Jarkko Nikula wrote: > Hi > > On 05/15/2018 01:20 PM, Jarkko Nikula wrote: >> >> On 05/15/2018 06:22 AM, Chris Chiu wrote: >>> >>> What if I change the 120MHz to 180MHz and then make sure that the I2C >>> operates >>> in target FS mode frequency 400kHz via scope? Would there be any side >>> effect? >>> Maybe some other busses frequency could be also affected and causing some >>> other >>> component malfunction? >>> >> Should be safe. It is only clock rate information when registering a fixed >> clock with known rate in intel-lpss.c and i2c-designware uses that info when >> calculating the timing parameters. I.e. it doesn't change any internal >> clocks. >> >> I'm trying to find a contact who can confirm what is the expected rate of >> I2C input clock and is it common to all Cannon Lake HW. >> > I got confirmation that input clock is actually even higher 216 Mhz. > > While checking does it cover all of those CNL CNL-LP and CNL-H PCI IDs may I > add your Jian-Hong, Chris and Daniel email addresses to Repored-by tags in a > fix patch? > > -- > Jarkko No problem. Thanks