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From:   Bharat Kumar Gogada <bharatku@xilinx.com>
To:     Keith Busch <keith.busch@linux.intel.com>
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Subject: RE: INTMS/INTMC not being used in NVME interrupt handling
Thread-Topic: INTMS/INTMC not being used in NVME interrupt handling
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Date:   Thu, 17 May 2018 11:15:59 +0000
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> > Hi,
> >
> > As per NVME specification:
> > 7.5.1.1 Host Software Interrupt Handling It is recommended that host
> > software utilize the Interrupt Mask Set and Interrupt Mask Clear
> > (INTMS/INTMC) registers to efficiently handle interrupts when configure=
d
> to use pin based or MSI messages.
> >
> > In kernel 4.14, drivers/nvme/host/pci.c function nvme_isr doesn't  use
> > these registers.
> >
> > Any reason why these registers are not used in nvme interrupt handler ?
>=20
> I think you've answered your own question: we process completions in the
> interrupt context. The interrupt is already masked at the CPU level in th=
is
> context, so there should be no reason to mask them at the device level.
>=20
> > Why NVMe driver is not using any bottom half and processing all
> > completion queues in interrupt handler ?
>=20
> Performance.
Thanks keith.=20
Currently driver isn't setting any Coalesce count. =20
So the NVMe card will raise interrupt for every single completion queue ?

For legacy interrupt for each CQ=20
CQ-> ASSERT_INTA-> DOORBELL-> DEASSERT_INTA is this flow correct ?

Is the following flow valid
CQ1->ASSERT_INTA->CQ2/CQ3->Doorbell->DEASSERT_INTA ?

When using legacy interrupts, if CQ1 is sent followed by ASSERT_INTA, can t=
he EP send=20
another CQ2,CQ3.. before DEASSERT_INTA of CQ1 is generated?

Regards,
Bharat