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[209.132.180.67]) by mx.google.com with ESMTP id s1-v6si5701320pfb.39.2018.05.17.09.25.02; Thu, 17 May 2018 09:25:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=MnvWmV56; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751977AbeEQQXr (ORCPT + 99 others); Thu, 17 May 2018 12:23:47 -0400 Received: from mail.kernel.org ([198.145.29.99]:41112 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751280AbeEQQXo (ORCPT ); Thu, 17 May 2018 12:23:44 -0400 Received: from mail-qt0-f179.google.com (mail-qt0-f179.google.com [209.85.216.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 0EE7620857; Thu, 17 May 2018 16:23:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1526574224; bh=5D07EnPhmNEjlHj+O1P8UBH5nsDmNaFbhF5qFanau2s=; h=In-Reply-To:References:From:Date:Subject:To:Cc:From; b=MnvWmV56iReVMrT0FYUAtYdMOE5sCQSFqimUwsEexsUnPJsKuklqA93e8BceWem8r cEy1v++N5yjsC3V42FljyP3UDO2QWVEQ6OQ9fgBg/6Zc9PZQ/fYe9rxkSHktlZbHEa rhLIgU8sAPnOoTLV8TJ+dPsZWk9Xyw5QQmb7dWUg= Received: by mail-qt0-f179.google.com with SMTP id m5-v6so6538290qti.1; Thu, 17 May 2018 09:23:44 -0700 (PDT) X-Gm-Message-State: ALKqPwfLtq2CoKhgwgOz9Xf2wH+vv90RVKaFk1HMc8ZTRa2nd0HlyEoM HRz+0CyaIIt/BsDrJmg1Yml6hJugsd7zWhEW6w== X-Received: by 2002:ac8:396f:: with SMTP id t44-v6mr5922085qtb.22.1526574223164; Thu, 17 May 2018 09:23:43 -0700 (PDT) MIME-Version: 1.0 Received: by 10.12.155.2 with HTTP; Thu, 17 May 2018 09:23:22 -0700 (PDT) In-Reply-To: References: From: Rob Herring Date: Thu, 17 May 2018 11:23:22 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v6 6/9] dt-bindings: counter: Document stm32 quadrature encoder To: William Breathitt Gray Cc: Jonathan Cameron , Benjamin Gaignard , Fabrice Gasnier , linux-iio@vger.kernel.org, "linux-kernel@vger.kernel.org" , devicetree@vger.kernel.org, "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , Mark Rutland Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 16, 2018 at 12:51 PM, William Breathitt Gray wrote: > From: Benjamin Gaignard v6? Where's v1-v5? > Add bindings for STM32 Timer quadrature encoder. > It is a sub-node of STM32 Timer which implement the > counter part of the hardware. > > Cc: Rob Herring > Cc: Mark Rutland > Signed-off-by: Benjamin Gaignard > Signed-off-by: William Breathitt Gray > --- > .../bindings/counter/stm32-timer-cnt.txt | 26 +++++++++++++++++++ > .../devicetree/bindings/mfd/stm32-timers.txt | 7 +++++ > 2 files changed, 33 insertions(+) > create mode 100644 Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt > > diff --git a/Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt b/Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt > new file mode 100644 > index 000000000000..377728128bef > --- /dev/null > +++ b/Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt > @@ -0,0 +1,26 @@ > +STMicroelectronics STM32 Timer quadrature encoder > + > +STM32 Timer provides quadrature encoder counter mode to detect 'mode' does not sound like a sub-block of the timers block. > +angular position and direction of rotary elements, > +from IN1 and IN2 input signals. > + > +Must be a sub-node of an STM32 Timer device tree node. > +See ../mfd/stm32-timers.txt for details about the parent node. > + > +Required properties: > +- compatible: Must be "st,stm32-timer-counter". > +- pinctrl-names: Set to "default". > +- pinctrl-0: List of phandles pointing to pin configuration nodes, > + to set IN1/IN2 pins in mode of operation for Low-Power > + Timer input on external pin. > + > +Example: > + timers@40010000 { > + compatible = "st,stm32-timers"; > + ... > + counter { > + compatible = "st,stm32-timer-counter"; Is there only 1? How is the counter addressed? > + pinctrl-names = "default"; > + pinctrl-0 = <&tim1_in_pins>; > + }; > + };